From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hans Zhang <hans.zhang@cixtech.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com,
fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
Date: Mon, 30 Jun 2025 13:14:27 +0200 [thread overview]
Message-ID: <5b182268-d64c-424c-9ada-0c3f120d2817@kernel.org> (raw)
In-Reply-To: <bb4889ca-ec99-4677-9ddc-28905b6fcc14@cixtech.com>
On 30/06/2025 10:29, Hans Zhang wrote:
>>> +
>>> + num-lanes:
>>> + maximum: 8
>>> +
>>> + ranges:
>>> + maxItems: 3
>>> +
>>> + msi-map:
>>> + maxItems: 1
>>> +
>>> + vendor-id:
>>> + const: 0x1f6c
>>
>> Why? This is implied by compatible.
>
> Because when we designed the SOC RTL, it was not set to the vendor id
> and device id of our company. We are members of PCI-SIG. So we need to
> set the vendor id and device id in the Root Port driver. Otherwise, the
> output of lspci will be displayed incorrectly.
Please read carefully. Previous discussions were also pointlessly
ping-ponging on irrelevant arguments. Did I suggest you do not have to
set it in root port driver? No. If this is const here, this is implied
by compatible and completely redundant, because your driver knows this
value already. It already has all the information to deduce this value
from the compatible.
>
>>
>>> +
>>> + device-id:
>>> + enum:
>>> + - 0x0001
>>
>> Why? This is implied by compatible.
>
> The reason is the same as above.
>
>>
>>> +
>>> + cdns,no-inbound-bar:
>>
>> That's not a cdns binding, so wrong prefix.
>
> It will be added to Cadence's Doc. I will add a separate patch. What do
> you think?
>
>>
>>> + description: |
>>
>> Do not need '|' unless you need to preserve formatting.
>
> Will delete '|'.
>
>>
>>> + Indicates the PCIe controller does not require an inbound BAR region.
>>
>> And anyway this is implied by compatible, drop.
>>
>
> Because Cadence core driver has this judgment, the latest code of the
> current linux master all has this process. As follows:
> int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
> cdns_pcie_host_init_address_translation(rc);
> cdns_pcie_host_map_dma_ranges(rc);
> cdns_pcie_host_bar_ib_config
And you cannot fix or change drivers? How does it matter for discussion
here?
>
> So this attribute has been added here, or is there a better way?
Of course, like every other driver in Linux kernel. This is FIXED for
your platform, so set it in your CIX driver.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-06-30 11:14 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-30 4:15 [PATCH v5 00/14] Enhance the PCIe controller driver hans.zhang
2025-06-30 4:15 ` [PATCH v5 01/14] dt-bindings: pci: cadence: Extend compatible for new RP configuration hans.zhang
2025-06-30 7:30 ` Krzysztof Kozlowski
2025-06-30 8:02 ` Hans Zhang
2025-06-30 8:06 ` Manikandan Karunakaran Pillai
2025-06-30 11:11 ` Krzysztof Kozlowski
2025-07-01 11:56 ` Manikandan Karunakaran Pillai
2025-07-02 20:20 ` Krzysztof Kozlowski
2025-07-03 1:35 ` Manikandan Karunakaran Pillai
2025-07-03 6:55 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 02/14] dt-bindings: pci: cadence: Extend compatible for new EP configuration hans.zhang
2025-06-30 7:27 ` Krzysztof Kozlowski
2025-06-30 8:03 ` Hans Zhang
2025-06-30 10:28 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 03/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-06-30 4:15 ` [PATCH v5 04/14] PCI: cadence: Add register definitions for HPA(High Perf Architecture) hans.zhang
2025-06-30 4:15 ` [PATCH v5 05/14] PCI: cadence: Split PCIe EP support into common and specific functions hans.zhang
2025-06-30 4:15 ` [PATCH v5 06/14] PCI: cadence: Split PCIe RP " hans.zhang
2025-06-30 4:15 ` [PATCH v5 07/14] PCI: cadence: Split the common functions for PCIE controller support hans.zhang
2025-06-30 4:15 ` [PATCH v5 08/14] PCI: cadence: Add support for High Performance Arch(HPA) controller hans.zhang
2025-06-30 4:15 ` [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform hans.zhang
2025-06-30 4:15 ` [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-06-30 5:36 ` Rob Herring (Arm)
2025-06-30 5:56 ` Hans Zhang
2025-06-30 7:26 ` Krzysztof Kozlowski
2025-06-30 8:29 ` Hans Zhang
2025-06-30 11:14 ` Krzysztof Kozlowski [this message]
2025-06-30 15:30 ` Hans Zhang
2025-07-02 20:23 ` Krzysztof Kozlowski
2025-07-03 1:47 ` Hans Zhang
2025-07-14 7:43 ` Krzysztof Kozlowski
2025-07-14 8:03 ` Hans Zhang
2025-07-15 6:40 ` Krzysztof Kozlowski
2025-07-15 6:46 ` Hans Zhang
2025-06-30 15:54 ` Hans Zhang
2025-07-02 20:28 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-06-30 4:15 ` [PATCH v5 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-06-30 7:29 ` Krzysztof Kozlowski
2025-06-30 8:06 ` Hans Zhang
2025-06-30 4:16 ` [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-06-30 7:33 ` Krzysztof Kozlowski
2025-06-30 8:44 ` Hans Zhang
2025-06-30 4:16 ` [PATCH v5 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-06-30 7:32 ` Krzysztof Kozlowski
2025-06-30 8:08 ` Hans Zhang
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