From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hans Zhang <hans.zhang@cixtech.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com,
fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
Date: Wed, 2 Jul 2025 22:23:16 +0200 [thread overview]
Message-ID: <a7aac65e-848b-4bb3-bd52-963766410698@kernel.org> (raw)
In-Reply-To: <2b608302-c4a6-404d-9cc5-d1ab9a6712bd@cixtech.com>
On 30/06/2025 17:30, Hans Zhang wrote:
>
>
> On 2025/6/30 19:14, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On 30/06/2025 10:29, Hans Zhang wrote:
>>>>> +
>>>>> + num-lanes:
>>>>> + maximum: 8
>>>>> +
>>>>> + ranges:
>>>>> + maxItems: 3
>>>>> +
>>>>> + msi-map:
>>>>> + maxItems: 1
>>>>> +
>>>>> + vendor-id:
>>>>> + const: 0x1f6c
>>>>
>>>> Why? This is implied by compatible.
>>>
>>> Because when we designed the SOC RTL, it was not set to the vendor id
>>> and device id of our company. We are members of PCI-SIG. So we need to
>>> set the vendor id and device id in the Root Port driver. Otherwise, the
>>> output of lspci will be displayed incorrectly.
>>
>> Please read carefully. Previous discussions were also pointlessly
>> ping-ponging on irrelevant arguments. Did I suggest you do not have to
>> set it in root port driver? No. If this is const here, this is implied
>> by compatible and completely redundant, because your driver knows this
>> value already. It already has all the information to deduce this value
>> from the compatible.
>>
>>
> Dear Krzysztof,
>
> Thank you very much for your reply.
>
> These two attributes are also in the following document. Is this place
> out of date?
> Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
I would need to spend time to investigate that and I choose to do other
things instead. I am recently very grumpy on arguments "I found this
somewhere else". I found bugs somewhere else, so am I okay to introduce
them?
>
>
> We initially used the logic of Cadence common driver as follows:
> drivers/pci/controller/cadence/pcie-cadence-host.c
> of_property_read_u32(np, "vendor-id", &rc->vendor_id);
>
> of_property_read_u32(np, "device-id", &rc->device_id);
>
> So, can the code in Cadence be deleted?
Don't know. If this is ABI, then not.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-07-02 20:23 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-30 4:15 [PATCH v5 00/14] Enhance the PCIe controller driver hans.zhang
2025-06-30 4:15 ` [PATCH v5 01/14] dt-bindings: pci: cadence: Extend compatible for new RP configuration hans.zhang
2025-06-30 7:30 ` Krzysztof Kozlowski
2025-06-30 8:02 ` Hans Zhang
2025-06-30 8:06 ` Manikandan Karunakaran Pillai
2025-06-30 11:11 ` Krzysztof Kozlowski
2025-07-01 11:56 ` Manikandan Karunakaran Pillai
2025-07-02 20:20 ` Krzysztof Kozlowski
2025-07-03 1:35 ` Manikandan Karunakaran Pillai
2025-07-03 6:55 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 02/14] dt-bindings: pci: cadence: Extend compatible for new EP configuration hans.zhang
2025-06-30 7:27 ` Krzysztof Kozlowski
2025-06-30 8:03 ` Hans Zhang
2025-06-30 10:28 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 03/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-06-30 4:15 ` [PATCH v5 04/14] PCI: cadence: Add register definitions for HPA(High Perf Architecture) hans.zhang
2025-06-30 4:15 ` [PATCH v5 05/14] PCI: cadence: Split PCIe EP support into common and specific functions hans.zhang
2025-06-30 4:15 ` [PATCH v5 06/14] PCI: cadence: Split PCIe RP " hans.zhang
2025-06-30 4:15 ` [PATCH v5 07/14] PCI: cadence: Split the common functions for PCIE controller support hans.zhang
2025-06-30 4:15 ` [PATCH v5 08/14] PCI: cadence: Add support for High Performance Arch(HPA) controller hans.zhang
2025-06-30 4:15 ` [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform hans.zhang
2025-06-30 4:15 ` [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-06-30 5:36 ` Rob Herring (Arm)
2025-06-30 5:56 ` Hans Zhang
2025-06-30 7:26 ` Krzysztof Kozlowski
2025-06-30 8:29 ` Hans Zhang
2025-06-30 11:14 ` Krzysztof Kozlowski
2025-06-30 15:30 ` Hans Zhang
2025-07-02 20:23 ` Krzysztof Kozlowski [this message]
2025-07-03 1:47 ` Hans Zhang
2025-07-14 7:43 ` Krzysztof Kozlowski
2025-07-14 8:03 ` Hans Zhang
2025-07-15 6:40 ` Krzysztof Kozlowski
2025-07-15 6:46 ` Hans Zhang
2025-06-30 15:54 ` Hans Zhang
2025-07-02 20:28 ` Krzysztof Kozlowski
2025-06-30 4:15 ` [PATCH v5 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-06-30 4:15 ` [PATCH v5 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-06-30 7:29 ` Krzysztof Kozlowski
2025-06-30 8:06 ` Hans Zhang
2025-06-30 4:16 ` [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-06-30 7:33 ` Krzysztof Kozlowski
2025-06-30 8:44 ` Hans Zhang
2025-06-30 4:16 ` [PATCH v5 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-06-30 7:32 ` Krzysztof Kozlowski
2025-06-30 8:08 ` Hans Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a7aac65e-848b-4bb3-bd52-963766410698@kernel.org \
--to=krzk@kernel.org \
--cc=bhelgaas@google.com \
--cc=cix-kernel-upstream@cixtech.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fugang.duan@cixtech.com \
--cc=guoyin.chen@cixtech.com \
--cc=hans.zhang@cixtech.com \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=kwilczynski@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=mpillai@cadence.com \
--cc=peter.chen@cixtech.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®