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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Hans Zhang <hans.zhang@cixtech.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
	mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com,
	fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
	peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
Date: Wed, 2 Jul 2025 22:28:25 +0200	[thread overview]
Message-ID: <913b3a01-5610-4709-87c1-4e225df466d5@kernel.org> (raw)
In-Reply-To: <5e9ddbe4-c94c-4087-8b34-0407ea278888@cixtech.com>

On 30/06/2025 17:54, Hans Zhang wrote:
> 
> 
> On 2025/6/30 15:26, Krzysztof Kozlowski wrote:
>>> +  sky1,pcie-ctrl-id:
>>> +    description: |
>>> +      Specifies the PCIe controller instance identifier (0-4).
>> No, you don't get an instance ID. Drop the property and look how other
>> bindings encoded it (not sure about the purpose and you did not explain
>> it, so cannot advise).
> 
> 
> Dear Krzysztof,
> 
> Sorry, I missed your reply to this in the previous email.
> 
> Because our Root Port driver needs to support 5 PCIe ports, and the 
> register configuration and offset of each port are different, it is 
> necessary to know which port it is currently. Perhaps I can use the 
> following method and then delete this attribute.
> 
> aliases {
> 		......
> 		pcie_rc0 = &pcie_x8_rc;
> 		pcie_rc1 = &pcie_x4_rc;
> 		pcie_rc2 = &pcie_x2_rc;
> 		pcie_rc3 = &pcie_x1_0_rc;
> 		pcie_rc4 = &pcie_x1_1_rc;
> 		
> id = of_alias_get_id(dev->of_node, "pcie_rc");
I think Rob commented pretty strongly about aliases in this thread... or
was it other one? Maybe it was about Tesla FSD PCI PHY... huh, same pattern.

So no, you do not get your own aliases.

Explain the differences in the hardware. If the hardware is different,
then it warrants different compatibles or other properties. But you need
to explain these differences. What is there? Different number of lanes?
Different phy? We have properties for that, use these. Different speed?
All of them have their own properties already, so use them. Maybe
something else... Do the homework and look at schemas and dtschema (yes,
I know that I said other poor solutions are not excuse to copy them, but
look for good solutions).

Best regards,
Krzysztof

  reply	other threads:[~2025-07-02 20:28 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30  4:15 [PATCH v5 00/14] Enhance the PCIe controller driver hans.zhang
2025-06-30  4:15 ` [PATCH v5 01/14] dt-bindings: pci: cadence: Extend compatible for new RP configuration hans.zhang
2025-06-30  7:30   ` Krzysztof Kozlowski
2025-06-30  8:02     ` Hans Zhang
2025-06-30  8:06       ` Manikandan Karunakaran Pillai
2025-06-30 11:11         ` Krzysztof Kozlowski
2025-07-01 11:56           ` Manikandan Karunakaran Pillai
2025-07-02 20:20             ` Krzysztof Kozlowski
2025-07-03  1:35               ` Manikandan Karunakaran Pillai
2025-07-03  6:55                 ` Krzysztof Kozlowski
2025-06-30  4:15 ` [PATCH v5 02/14] dt-bindings: pci: cadence: Extend compatible for new EP configuration hans.zhang
2025-06-30  7:27   ` Krzysztof Kozlowski
2025-06-30  8:03     ` Hans Zhang
2025-06-30 10:28   ` Krzysztof Kozlowski
2025-06-30  4:15 ` [PATCH v5 03/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-06-30  4:15 ` [PATCH v5 04/14] PCI: cadence: Add register definitions for HPA(High Perf Architecture) hans.zhang
2025-06-30  4:15 ` [PATCH v5 05/14] PCI: cadence: Split PCIe EP support into common and specific functions hans.zhang
2025-06-30  4:15 ` [PATCH v5 06/14] PCI: cadence: Split PCIe RP " hans.zhang
2025-06-30  4:15 ` [PATCH v5 07/14] PCI: cadence: Split the common functions for PCIE controller support hans.zhang
2025-06-30  4:15 ` [PATCH v5 08/14] PCI: cadence: Add support for High Performance Arch(HPA) controller hans.zhang
2025-06-30  4:15 ` [PATCH v5 09/14] PCI: cadence: Add support for PCIe HPA controller platform hans.zhang
2025-06-30  4:15 ` [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-06-30  5:36   ` Rob Herring (Arm)
2025-06-30  5:56     ` Hans Zhang
2025-06-30  7:26   ` Krzysztof Kozlowski
2025-06-30  8:29     ` Hans Zhang
2025-06-30 11:14       ` Krzysztof Kozlowski
2025-06-30 15:30         ` Hans Zhang
2025-07-02 20:23           ` Krzysztof Kozlowski
2025-07-03  1:47             ` Hans Zhang
2025-07-14  7:43               ` Krzysztof Kozlowski
2025-07-14  8:03                 ` Hans Zhang
2025-07-15  6:40                   ` Krzysztof Kozlowski
2025-07-15  6:46                     ` Hans Zhang
2025-06-30 15:54     ` Hans Zhang
2025-07-02 20:28       ` Krzysztof Kozlowski [this message]
2025-06-30  4:15 ` [PATCH v5 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-06-30  4:15 ` [PATCH v5 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-06-30  7:29   ` Krzysztof Kozlowski
2025-06-30  8:06     ` Hans Zhang
2025-06-30  4:16 ` [PATCH v5 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-06-30  7:33   ` Krzysztof Kozlowski
2025-06-30  8:44     ` Hans Zhang
2025-06-30  4:16 ` [PATCH v5 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-06-30  7:32   ` Krzysztof Kozlowski
2025-06-30  8:08     ` Hans Zhang

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