* [PATCH 1/3] dt-bindings: connector: Add PCIe M.2 Mechanical Key B connector
2026-10-21 13:51 [PATCH 0/3] power: sequencing: pcie-m2: Add PCIe M.2 Key B connector support Krishna Chaitanya Chundru
@ 2026-10-21 13:51 ` Krishna Chaitanya Chundru
2026-10-21 15:44 ` Alexey Charkov
2026-10-21 13:51 ` [PATCH 2/3] power: sequencing: pcie-m2: Add support for PCIe M.2 Key B connectors Krishna Chaitanya Chundru
2026-10-21 13:51 ` [PATCH 3/3] arm64: dts: qcom: glymur-crd: Describe the PCIe M.2 Key B connector Krishna Chaitanya Chundru
2 siblings, 1 reply; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-21 13:51 UTC (permalink / raw)
To: Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, Bjorn Andersson,
Konrad Dybcio
Cc: linux-pci, devicetree, linux-kernel, linux-pm, linux-arm-msm,
Krishna Chaitanya Chundru
Add the devicetree binding for PCIe M.2 Mechanical Key B connector
defined in the PCI Express M.2 Specification, r4.2, sec 3.2.19.1. This
connector is used to attach WWAN Adapters to the host machine over
interfaces such as PCIe, USB3.1 Gen1, SSIC, or USB 2.0, selected by the
Adapter's configuration pins.
The connector provides a primary power supply of 3.3V/VBAT, along with
optional GPIO signals for WWAN-specific power/radio control:
FULL_CARD_POWER_OFF#, RESET#, W_DISABLE1#/2#, WAKE_ON_WWAN#, and DPR.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
.../bindings/connector/pcie-m2-b-connector.yaml | 146 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 147 insertions(+)
diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml
new file mode 100644
index 000000000000..a7f4bcbc5119
--- /dev/null
+++ b/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/connector/pcie-m2-b-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCIe M.2 Mechanical Key B Connector
+
+maintainers:
+ - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
+
+description:
+ A PCIe M.2 B connector node represents a physical PCIe M.2 Mechanical Key B
+ connector. Mechanical Key B connectors are used to connect WWAN devices to
+ the host machine over interfaces like PCIe, USB3.1 Gen1, SSIC, or USB 2.0,
+ selected by the Adapter's configuration pins.
+
+properties:
+ compatible:
+ const: pcie-m2-b-connector
+
+ vpcie3v3-supply:
+ description: A phandle to the regulator for the 3.3v/VBAT supply.
+
+ full-card-power-off-gpios:
+ description: GPIO output to FULL_CARD_POWER_OFF# signal. This signal is
+ used by the host system to turn off the entire Adapter. Refer, PCI
+ Express M.2 Specification r4.0, sec 3.2.13.1 for more details.
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO output to RESET# signal. This signal is used by the
+ host system to place the WWAN Adapter into a power-on reset condition.
+ Refer, PCI Express M.2 Specification r4.0, sec 3.2.13.2 for more
+ details.
+ maxItems: 1
+
+ w-disable1-gpios:
+ description: GPIO output to W_DISABLE1# signal. This signal is used by
+ the host system to disable the WWAN radio on the Adapter. Refer, PCI
+ Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
+ maxItems: 1
+
+ w-disable2-gpios:
+ description: GPIO output to W_DISABLE2# signal (default function of
+ GPIO_10). This signal is used by the host system to disable a second
+ radio on the Adapter. Refer, PCI Express M.2 Specification r4.0,
+ sec 3.1.12.3 for more details.
+ maxItems: 1
+
+ wowwan-gpios:
+ description: GPIO input to WAKE_ON_WWAN# (WoWWAN#) signal. The Adapter
+ asserts this signal to wake up the host system. Refer, PCI Express M.2
+ Specification r4.0, sec 3.2.13.3.6 for more details.
+ maxItems: 1
+
+ dpr-gpios:
+ description: GPIO output to the Dynamic Power Reduction (DPR) signal.
+ This signal is provided by a host system proximity sensor to the
+ Adapter to trigger a reduction in the radio transmit output power to
+ meet regulatory SAR requirements. Refer, PCI Express M.2 Specification
+ r4.0, sec 3.2.13.4 for more details.
+ maxItems: 1
+
+ clocks:
+ description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
+ the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
+ more details.
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: OF graph bindings modeling the interfaces exposed on the
+ connector. Since a single connector can have multiple interfaces, every
+ interface has an assigned OF graph port number as described below.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: PCIe interface for WWAN
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: SSIC interface for WWAN
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: USB 2.0 interface for WWAN
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: USB3.1 Gen1 interface for WWAN
+
+ anyOf:
+ - required:
+ - port@0
+ - required:
+ - port@1
+ - required:
+ - port@3
+
+required:
+ - compatible
+ - vpcie3v3-supply
+
+additionalProperties: false
+
+examples:
+ # PCI M.2 Key B connector for WWAN with PCIe interface
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ connector {
+ compatible = "pcie-m2-b-connector";
+ vpcie3v3-supply = <&vreg_wwan>;
+ full-card-power-off-gpios = <&tlmm 121 GPIO_ACTIVE_LOW>;
+ w-disable1-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
+ wowwan-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&pcie6_port0_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usb_hs_ep>;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b5cab72d851..22cfd2b72e1a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21794,6 +21794,7 @@ PCIE M.2 POWER SEQUENCING
M: Manivannan Sadhasivam <mani@kernel.org>
L: linux-pci@vger.kernel.org
S: Maintained
+F: Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml
F: Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml
F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
F: drivers/power/sequencing/pwrseq-pcie-m2.c
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/3] power: sequencing: pcie-m2: Add support for PCIe M.2 Key B connectors
2026-10-21 13:51 [PATCH 0/3] power: sequencing: pcie-m2: Add PCIe M.2 Key B connector support Krishna Chaitanya Chundru
2026-10-21 13:51 ` [PATCH 1/3] dt-bindings: connector: Add PCIe M.2 Mechanical Key B connector Krishna Chaitanya Chundru
@ 2026-10-21 13:51 ` Krishna Chaitanya Chundru
2026-10-21 13:51 ` [PATCH 3/3] arm64: dts: qcom: glymur-crd: Describe the PCIe M.2 Key B connector Krishna Chaitanya Chundru
2 siblings, 0 replies; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-21 13:51 UTC (permalink / raw)
To: Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, Bjorn Andersson,
Konrad Dybcio
Cc: linux-pci, devicetree, linux-kernel, linux-pm, linux-arm-msm,
Krishna Chaitanya Chundru
Add support for handling the power sequence of the PCIe M.2 Key B
connectors. These connectors are used to attach WWAN Adapters to the
host machine over interfaces such as PCIe, USB3.1 Gen1, SSIC, or USB
2.0.
Currently, this driver only supports driving the 3.3V/VBAT power
supply along with the FULL_CARD_POWER_OFF#, RESET#, and W_DISABLE1#/2#
GPIOs as a single "pcie" target, since Key B Adapters expose only a
discoverable PCIe/USB interface and no non-discoverable bus (unlike
Key E's UART-attached Bluetooth device), so no serdev creation is
needed. The optional WAKE_ON_WWAN# and DPR signals are not currently
supported.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/power/sequencing/pwrseq-pcie-m2.c | 82 +++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequencing/pwrseq-pcie-m2.c
index e42e85f47629..62185bf30d73 100644
--- a/drivers/power/sequencing/pwrseq-pcie-m2.c
+++ b/drivers/power/sequencing/pwrseq-pcie-m2.c
@@ -39,6 +39,8 @@ struct pwrseq_pcie_m2_ctx {
struct notifier_block nb;
struct gpio_desc *w_disable1_gpio;
struct gpio_desc *w_disable2_gpio;
+ struct gpio_desc *full_card_power_off_gpio;
+ struct gpio_desc *reset_gpio;
struct device *dev;
struct list_head pci_devices;
struct mutex list_lock;
@@ -111,6 +113,53 @@ static const struct pwrseq_unit_data pwrseq_pcie_m2_e_pcie_unit_data = {
.disable = pwrseq_pci_m2_e_pcie_disable,
};
+static int pwrseq_pci_m2_b_pcie_enable(struct pwrseq_device *pwrseq)
+{
+ struct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);
+ int ret;
+
+ ret = gpiod_set_value_cansleep(ctx->full_card_power_off_gpio, 0);
+ if (ret)
+ return ret;
+
+ ret = gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ ret = gpiod_set_value_cansleep(ctx->w_disable1_gpio, 0);
+ if (ret)
+ return ret;
+
+ return gpiod_set_value_cansleep(ctx->w_disable2_gpio, 0);
+}
+
+static int pwrseq_pci_m2_b_pcie_disable(struct pwrseq_device *pwrseq)
+{
+ struct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);
+ int ret;
+
+ ret = gpiod_set_value_cansleep(ctx->w_disable2_gpio, 1);
+ if (ret)
+ return ret;
+
+ ret = gpiod_set_value_cansleep(ctx->w_disable1_gpio, 1);
+ if (ret)
+ return ret;
+
+ ret = gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ return gpiod_set_value_cansleep(ctx->full_card_power_off_gpio, 1);
+}
+
+static const struct pwrseq_unit_data pwrseq_pcie_m2_b_pcie_unit_data = {
+ .name = "pcie-enable",
+ .deps = pwrseq_pcie_m2_unit_deps,
+ .enable = pwrseq_pci_m2_b_pcie_enable,
+ .disable = pwrseq_pci_m2_b_pcie_disable,
+};
+
static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data = {
.name = "pcie-enable",
.deps = pwrseq_pcie_m2_unit_deps,
@@ -140,6 +189,11 @@ static const struct pwrseq_target_data pwrseq_pcie_m2_e_pcie_target_data = {
.post_enable = pwrseq_pcie_m2_e_pwup_delay,
};
+static const struct pwrseq_target_data pwrseq_pcie_m2_b_pcie_target_data = {
+ .name = "pcie",
+ .unit = &pwrseq_pcie_m2_b_pcie_unit_data,
+};
+
static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = {
.name = "pcie",
.unit = &pwrseq_pcie_m2_m_pcie_unit_data,
@@ -151,6 +205,11 @@ static const struct pwrseq_target_data *pwrseq_pcie_m2_e_targets[] = {
NULL
};
+static const struct pwrseq_target_data *pwrseq_pcie_m2_b_targets[] = {
+ &pwrseq_pcie_m2_b_pcie_target_data,
+ NULL
+};
+
static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] = {
&pwrseq_pcie_m2_m_pcie_target_data,
NULL
@@ -160,6 +219,10 @@ static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_e_of_data = {
.targets = pwrseq_pcie_m2_e_targets,
};
+static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_b_of_data = {
+ .targets = pwrseq_pcie_m2_b_targets,
+};
+
static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data = {
.targets = pwrseq_pcie_m2_m_targets,
};
@@ -534,6 +597,21 @@ static int pwrseq_pcie_m2_probe(struct platform_device *pdev)
goto err_free_regulators;
}
+ ctx->full_card_power_off_gpio = devm_gpiod_get_optional(dev, "full-card-power-off",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->full_card_power_off_gpio)) {
+ ret = dev_err_probe(dev, PTR_ERR(ctx->full_card_power_off_gpio),
+ "Failed to get the FULL_CARD_POWER_OFF# GPIO\n");
+ goto err_free_regulators;
+ }
+
+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset_gpio)) {
+ ret = dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
+ "Failed to get the RESET# GPIO\n");
+ goto err_free_regulators;
+ }
+
config.parent = dev;
config.owner = THIS_MODULE;
config.drvdata = ctx;
@@ -598,6 +676,10 @@ static const struct of_device_id pwrseq_pcie_m2_of_match[] = {
.compatible = "pcie-m2-e-connector",
.data = &pwrseq_pcie_m2_e_of_data,
},
+ {
+ .compatible = "pcie-m2-b-connector",
+ .data = &pwrseq_pcie_m2_b_of_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match);
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: dts: qcom: glymur-crd: Describe the PCIe M.2 Key B connector
2026-10-21 13:51 [PATCH 0/3] power: sequencing: pcie-m2: Add PCIe M.2 Key B connector support Krishna Chaitanya Chundru
2026-10-21 13:51 ` [PATCH 1/3] dt-bindings: connector: Add PCIe M.2 Mechanical Key B connector Krishna Chaitanya Chundru
2026-10-21 13:51 ` [PATCH 2/3] power: sequencing: pcie-m2: Add support for PCIe M.2 Key B connectors Krishna Chaitanya Chundru
@ 2026-10-21 13:51 ` Krishna Chaitanya Chundru
2026-10-21 14:06 ` Konrad Dybcio
2 siblings, 1 reply; 6+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-10-21 13:51 UTC (permalink / raw)
To: Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski, Bjorn Andersson,
Konrad Dybcio
Cc: linux-pci, devicetree, linux-kernel, linux-pm, linux-arm-msm,
Krishna Chaitanya Chundru
The Glymur CRD has a WWAN M.2 slot connected to PCIe6. Currently the
vreg_wwan supply is described directly on the PCIe6 host bridge. As a
result, the supply follows the PCIe controller power state and is turned
off when the controller is powered down, regardless of the requirements
of the device connected to the slot.
Move control of the WWAN supply to the generic
pci-pwrctrl-slot/pwrseq-pcie-m2 framework. This allows slot power to be
coordinated with PCI device power-management requirements and keeps the
supply enabled when required by the PCI device, such as for PME-based
wake-up.
Describe the slot as a PCIe M.2 Mechanical Key B connector and link it
to the PCIe6 Root Port using a graph port/endpoint pair, as required by
the pcie-m2-b-connector binding.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index e27c697e3170..73de60b0d0e5 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -237,6 +237,27 @@ vreg_wwan: regulator-wwan {
pinctrl-names = "default";
};
+ wwan-connector {
+ compatible = "pcie-m2-b-connector";
+ vpcie3v3-supply = <&vreg_wwan>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wwan_m2_pcie_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&pcie6_port0_ep>;
+ };
+ };
+ };
+ };
+
sound {
compatible = "qcom,glymur-sndcard";
model = "GLYMUR-CRD";
@@ -810,8 +831,6 @@ &pcie5_port0 {
};
&pcie6 {
- vddpe-3v3-supply = <&vreg_wwan>;
-
pinctrl-0 = <&pcie6_default>;
pinctrl-names = "default";
@@ -828,6 +847,12 @@ &pcie6_phy {
&pcie6_port0 {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+
+ port {
+ pcie6_port0_ep: endpoint {
+ remote-endpoint = <&wwan_m2_pcie_ep>;
+ };
+ };
};
&pmh0110_f_e1_gpios {
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread