[PATCH v2 0/3] SM8450 QoL changes (dispcc)

[PATCH v2 0/3] SM8450 QoL changes (dispcc)

[Esteban Urrutia via B4 Relay]

These patches are mainly focused on getting a flickerless boot process
on SM8475 based devices.

Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
Changes in v2:
- Split series in subseries (dispcc, dts, qmp, smmu)
- Migrate to qcom_cc_driver_data (Konrad)
- Split mdss patch into 3 patches
- Use Fixes tag where applicable (Krzysztof)
- Link to v1: https://patch.msgid.link/20260622-sm8450-qol-v1-0-37e2ee8df9da@proton.me

---
Esteban Urrutia (3):
      clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops
      clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data
      clk: qcom: dispcc-sm8450: Keep pll types as is for SM8475

 drivers/clk/qcom/dispcc-sm8450.c | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)
---
base-commit: bee763d5f341b99cf472afeb508d4988f62a6ca1
change-id: 20260711-sm8450-qol-dispcc-09b2951d25b0

Best regards,
--  
Esteban Urrutia <esteuwu@proton.me>

[PATCH v2 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops

[Esteban Urrutia via B4 Relay]

From: Esteban Urrutia <esteuwu@proton.me>

If the clock frequency is changed at registration time, a flicker will be
visible at boot.
Switching to clk_rcg2_shared_no_init_park_ops fixes this.

Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450")
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
 drivers/clk/qcom/dispcc-sm8450.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 3af120e54cdd..c7e04bd315d5 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -613,7 +613,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 		.parent_data = disp_cc_parent_data_5,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_shared_ops,
+		.ops = &clk_rcg2_shared_no_init_park_ops,
 	},
 };
 

-- 
2.55.0

[PATCH v2 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data

[Esteban Urrutia via B4 Relay]

From: Esteban Urrutia <esteuwu@proton.me>

Migrate to qcom_cc_driver_data, which is used by other clock controller
drivers.

Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
 drivers/clk/qcom/dispcc-sm8450.c | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index c7e04bd315d5..07f22b5b5ee5 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -1778,6 +1778,22 @@ static const struct regmap_config disp_cc_sm8450_regmap_config = {
 	.fast_io = true,
 };
 
+static struct clk_alpha_pll *disp_cc_sm8450_plls[] = {
+	&disp_cc_pll0,
+	&disp_cc_pll1,
+};
+
+static const u32 disp_cc_sm8450_critical_cbcrs[] = {
+	0xe05c, /* DISP_CC_XO_CLK */
+};
+
+static const struct qcom_cc_driver_data disp_cc_sm8450_driver_data = {
+	.alpha_plls = disp_cc_sm8450_plls,
+	.num_alpha_plls = ARRAY_SIZE(disp_cc_sm8450_plls),
+	.clk_cbcrs = disp_cc_sm8450_critical_cbcrs,
+	.num_clk_cbcrs = ARRAY_SIZE(disp_cc_sm8450_critical_cbcrs),
+};
+
 static const struct qcom_cc_desc disp_cc_sm8450_desc = {
 	.config = &disp_cc_sm8450_regmap_config,
 	.clks = disp_cc_sm8450_clocks,
@@ -1786,6 +1802,7 @@ static const struct qcom_cc_desc disp_cc_sm8450_desc = {
 	.num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),
 	.gdscs = disp_cc_sm8450_gdscs,
 	.num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),
+	.driver_data = &disp_cc_sm8450_driver_data,
 };
 
 static const struct of_device_id disp_cc_sm8450_match_table[] = {
@@ -1823,19 +1840,16 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
 		disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
 		disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
 
-		clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config);
-		clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config);
+		disp_cc_pll0.config = &sm8475_disp_cc_pll0_config;
+		disp_cc_pll1.config = &sm8475_disp_cc_pll1_config;
 	} else {
-		clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
-		clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+		disp_cc_pll0.config = &disp_cc_pll0_config;
+		disp_cc_pll1.config = &disp_cc_pll1_config;
 	}
 
 	/* Enable clock gating for MDP clocks */
 	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
 
-	/* Keep some clocks always-on */
-	qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
-
 	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);
 	if (ret)
 		goto err_put_rpm;

-- 
2.55.0

[PATCH v2 3/3] clk: qcom: dispcc-sm8450: Keep pll types as is for SM8475

[Esteban Urrutia via B4 Relay]

From: Esteban Urrutia <esteuwu@proton.me>

While using an OLE PLL type is correct according to downstream code, this
results in the display flickering at boot for SM8475 because downstream
uses EVO type configurations for both clocks, while, for some reason,
upstream uses EVO type configurations for SM8450 and OLE type
configurations for SM8475.
So far, no regressions have been observed and the display no longer
flickers.

Fixes: 7c0e8764dc33 ("clk: qcom: dispcc-sm8450: Add SM8475 support")
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
---
 drivers/clk/qcom/dispcc-sm8450.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 07f22b5b5ee5..2c0edc23eeb1 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -1833,11 +1833,9 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
 
 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) {
 		/* Update DISPCC PLL0 */
-		disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
 		disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init;
 
 		/* Update DISPCC PLL1 */
-		disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
 		disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
 
 		disp_cc_pll0.config = &sm8475_disp_cc_pll0_config;

-- 
2.55.0

Re: [PATCH v2 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data

[Konrad Dybcio]

On 7/12/26 5:10 AM, Esteban Urrutia via B4 Relay wrote:
> From: Esteban Urrutia <esteuwu@proton.me>
> 
> Migrate to qcom_cc_driver_data, which is used by other clock controller
> drivers.
> 
> Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
> ---

[...]

>  	/* Enable clock gating for MDP clocks */
>  	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);

This would ideally become regmap_set_bits(..., BIT(4)) in desc->clk_regs_configure

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops

[Konrad Dybcio]

On 7/12/26 5:10 AM, Esteban Urrutia via B4 Relay wrote:
> From: Esteban Urrutia <esteuwu@proton.me>
> 
> If the clock frequency is changed at registration time, a flicker will be
> visible at boot.
> Switching to clk_rcg2_shared_no_init_park_ops fixes this.
> 
> Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450")
> Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 3/3] clk: qcom: dispcc-sm8450: Keep pll types as is for SM8475

[Konrad Dybcio]

On 7/12/26 5:10 AM, Esteban Urrutia via B4 Relay wrote:
> From: Esteban Urrutia <esteuwu@proton.me>
> 
> While using an OLE PLL type is correct according to downstream code, this
> results in the display flickering at boot for SM8475 because downstream
> uses EVO type configurations for both clocks, while, for some reason,
> upstream uses EVO type configurations for SM8450 and OLE type
> configurations for SM8475.
> So far, no regressions have been observed and the display no longer
> flickers.

No, these are two separate hardware designs and you can't mix the
configuration like that just because it so happens to circumvent a bug.

Taking a peek at clk_lucid_evo_pll_configure, there's an early bailout:

if (trion_pll_is_enabled(pll, regmap)) {
	pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
	return;
}

I think it should be fine to copy-paste it as-is for LUCID_OLE. Please
check if that resolves your issue.

Konrad

Re: [PATCH v2 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data

[Esteban Urrutia]

On 7/13/26 6:47 AM, Konrad Dybcio wrote:
> [...]
> 
>>  	/* Enable clock gating for MDP clocks */
>>  	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
> 
> This would ideally become regmap_set_bits(..., BIT(4)) in desc->clk_regs_configure
Will do in v3 :)

Regards,
Esteban

Re: [PATCH v2 3/3] clk: qcom: dispcc-sm8450: Keep pll types as is for SM8475

[Esteban Urrutia]

On 7/13/26 6:57 AM, Konrad Dybcio wrote:
> No, these are two separate hardware designs and you can't mix the
> configuration like that just because it so happens to circumvent a bug.
> 
> Taking a peek at clk_lucid_evo_pll_configure, there's an early bailout:
> 
> if (trion_pll_is_enabled(pll, regmap)) {
> 	pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
> 	return;
> }
> 
> I think it should be fine to copy-paste it as-is for LUCID_OLE. Please
> check if that resolves your issue.
Indeed, this solves the issue and the display no longer glitches out at
boot.
Will correct in v3; thanks for pointing me in the right direction.

Regards,
Esteban