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From: "Arnd Bergmann" <arnd@arndb.de>
To: "Ryan Chen" <ryan_chen@aspeedtech.com>,
	BMC-SW <BMC-SW@aspeedtech.com>, "Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Joel Stanley" <joel@jms.id.au>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Jeremy Kerr" <jk@codeconstruct.com.au>,
	"Lee Jones" <lee@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Bjorn Andersson" <bjorn.andersson@oss.qualcomm.com>,
	"Geert Uytterhoeven" <geert@linux-m68k.org>,
	"Nishanth Menon" <nm@ti.com>,
	"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
	"Taniya Das" <quic_tdas@quicinc.com>,
	"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Kuninori Morimoto" <kuninori.morimoto.gx@renesas.com>,
	"Eric Biggers" <ebiggers@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree
Date: Fri, 24 Oct 2025 09:02:34 +0200	[thread overview]
Message-ID: <66d0dc8f-553a-41b0-a9af-e058bc39dd94@app.fastmail.com> (raw)
In-Reply-To: <TY2PPF5CB9A1BE6CF8336D211641A18E2DEF2F1A@TY2PPF5CB9A1BE6.apcprd06.prod.outlook.com>

On Fri, Oct 24, 2025, at 05:54, Ryan Chen wrote:
>> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device
>> tree
>> On Thu, Oct 23, 2025, at 09:37, Ryan Chen wrote:
>> >> > +	soc1: soc@14000000 {
>> >> > +		compatible = "simple-bus";
>> >> > +		#address-cells = <2>;
>> >> > +		#size-cells = <2>;
>> >> > +		ranges = <0x0 0x0 0x0 0x14000000 0x0 0x10000000>;
>> >>
>> >> This probably needs some explanation: why are there two 'soc@...'
>> >> devices? Is this literally two chips in the system, or are you
>> >> describing two buses inside of the same SoC?
>> >
>> > The AST2700 is two soc connection with a property bus.
>> > Sharing some decode registers. Each have it own ahb bus.
>> 
>> I don't understand your explanation,
>
> Let me clarify more clearly:
> The AST2700 is a dual-SoC architecture, consisting of two interconnected SoCs,
> referred to as SoC0 and SoC1. Each SoC has its own clock/reset domains. 
> They are connected through an internal "property bus", 
> which is Aspeed's internal interconnect providing shared
> address decoding and communication between the two SoCs.

Makes sense. Since this is a fairly unusual design, I would suggest
you add that explanation into the patch description for this
patch as well, so readers have a chance to find it when they look
at the file in the git history at a later point.

>> Since there is no corresponding driver change, I would keep the binding change
>> as a patch in this series.
>
> Sorry, I am wondering, I will follow Andrew advice. 
> Submit ast2700-mdio to net-next go out another thread.
> And put submit link in cover-letter in next version.
> Is it ok?

Yes

>> The version of the driver you are linking does not appear to use syscon, maybe
>> this is an artifact from a previous version?
>> 
>> If so, you can drop it. On the other hand, this does seem to be a classic syscon
>> device and keeping it marked that way is not harmful, just redundant if you
>> actually use the more specific compatible string.
>
> Sorry, I may not point right link
> https://patchwork.ozlabs.org/project/linux-aspeed/patch/20250829073030.2749482-4-billy_tsai@aspeedtech.com/
> aspeed_g7_soc0_pinctrl_probe -> aspeed_pinctrl_probe
> https://github.com/torvalds/linux/blob/master/drivers/pinctrl/aspeed/pinctrl-aspeed.c#L456
>
> That will use syscon to regmap.

Right, if that is the documented binding, I think keeping syscon in
the compatible list makes sense.

      Arnd

  reply	other threads:[~2025-10-24  7:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  7:05 [PATCH v6 0/6] Introduce ASPEED AST2700 BMC SoC Ryan Chen
2025-10-22  7:05 ` [PATCH v6 1/6] dt-bindings: arm: aspeed: Add AST2700 board compatible Ryan Chen
2025-10-22  7:05 ` [PATCH v6 2/6] arm64: Kconfig: Add Aspeed SoC family (ast27XX) Kconfig support Ryan Chen
2025-10-22  7:05 ` [PATCH v6 3/6] dt-bindings: mfd: aspeed,ast2x00-scu: allow #size-cells range Ryan Chen
2025-10-22  8:07   ` Krzysztof Kozlowski
2025-10-22  8:08   ` Krzysztof Kozlowski
2025-10-22  8:28     ` Ryan Chen
2025-10-22  7:05 ` [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Ryan Chen
2025-10-22 21:29   ` Arnd Bergmann
2025-10-23  7:37     ` Ryan Chen
2025-10-23 18:28       ` Andrew Lunn
2025-10-23 20:11       ` Arnd Bergmann
2025-10-24  3:54         ` Ryan Chen
2025-10-24  7:02           ` Arnd Bergmann [this message]
2025-10-24 12:28           ` Andrew Lunn
2025-10-25  3:08             ` Ryan Chen
2025-10-27  1:43               ` Andrew Lunn
2025-10-27  2:42                 ` Ryan Chen
2025-10-27 12:01                   ` Andrew Lunn
2025-10-27 12:53                     ` Geert Uytterhoeven
2025-10-29  2:38                       ` Ryan Chen
2025-10-29  9:52                         ` Geert Uytterhoeven
2025-10-29  2:31                     ` Ryan Chen
2025-10-29  7:26                       ` Arnd Bergmann
2025-10-29  9:50                         ` Geert Uytterhoeven
2025-10-30  2:30                           ` Ryan Chen
2025-10-30  9:19                             ` Arnd Bergmann
2025-11-05  0:35                               ` Ryan Chen
2025-10-24  7:56         ` Geert Uytterhoeven
2025-10-25  3:15           ` Ryan Chen
2025-10-22  7:05 ` [PATCH v6 5/6] arm64: dts: aspeed: Add AST2700 Evaluation Board Ryan Chen
2025-10-22  7:05 ` [PATCH v6 6/6] arm64: configs: Update defconfig for AST2700 platform support Ryan Chen

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