From: Andrew Lunn <andrew@lunn.ch>
To: Ryan Chen <ryan_chen@aspeedtech.com>
Cc: "Arnd Bergmann" <arnd@arndb.de>, BMC-SW <BMC-SW@aspeedtech.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Joel Stanley" <joel@jms.id.au>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Jeremy Kerr" <jk@codeconstruct.com.au>,
"Lee Jones" <lee@kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@oss.qualcomm.com>,
"Geert Uytterhoeven" <geert@linux-m68k.org>,
"Nishanth Menon" <nm@ti.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Taniya Das" <quic_tdas@quicinc.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Kuninori Morimoto" <kuninori.morimoto.gx@renesas.com>,
"Eric Biggers" <ebiggers@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree
Date: Mon, 27 Oct 2025 02:43:24 +0100 [thread overview]
Message-ID: <fdbc471f-514e-4521-b7a1-dcf6127d64ff@lunn.ch> (raw)
In-Reply-To: <TY2PPF5CB9A1BE6F3E95C7FD61CF4F90ECAF2FEA@TY2PPF5CB9A1BE6.apcprd06.prod.outlook.com>
> SoC0, referred to as the CPU die, contains a dual-core Cortex-A35
> cluster and two Cortex-M4 cores, along with its own clock/reset
> domains and high-speed peripheral set.
> SoC1, referred to as the I/O die, contains the Boot MCU and its own
> clock/reset domains and low-speed peripheral set, and is responsible
> for system boot and control functions.
So is the same .dtsi file shared by both systems? How do you partition
devices so each CPU cluster knows it has exclusive access to which
peripherals?
Seems like a fun system to play core wars on.
Andrew
next prev parent reply other threads:[~2025-10-27 1:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:05 [PATCH v6 0/6] Introduce ASPEED AST2700 BMC SoC Ryan Chen
2025-10-22 7:05 ` [PATCH v6 1/6] dt-bindings: arm: aspeed: Add AST2700 board compatible Ryan Chen
2025-10-22 7:05 ` [PATCH v6 2/6] arm64: Kconfig: Add Aspeed SoC family (ast27XX) Kconfig support Ryan Chen
2025-10-22 7:05 ` [PATCH v6 3/6] dt-bindings: mfd: aspeed,ast2x00-scu: allow #size-cells range Ryan Chen
2025-10-22 8:07 ` Krzysztof Kozlowski
2025-10-22 8:08 ` Krzysztof Kozlowski
2025-10-22 8:28 ` Ryan Chen
2025-10-22 7:05 ` [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Ryan Chen
2025-10-22 21:29 ` Arnd Bergmann
2025-10-23 7:37 ` Ryan Chen
2025-10-23 18:28 ` Andrew Lunn
2025-10-23 20:11 ` Arnd Bergmann
2025-10-24 3:54 ` Ryan Chen
2025-10-24 7:02 ` Arnd Bergmann
2025-10-24 12:28 ` Andrew Lunn
2025-10-25 3:08 ` Ryan Chen
2025-10-27 1:43 ` Andrew Lunn [this message]
2025-10-27 2:42 ` Ryan Chen
2025-10-27 12:01 ` Andrew Lunn
2025-10-27 12:53 ` Geert Uytterhoeven
2025-10-29 2:38 ` Ryan Chen
2025-10-29 9:52 ` Geert Uytterhoeven
2025-10-29 2:31 ` Ryan Chen
2025-10-29 7:26 ` Arnd Bergmann
2025-10-29 9:50 ` Geert Uytterhoeven
2025-10-30 2:30 ` Ryan Chen
2025-10-30 9:19 ` Arnd Bergmann
2025-11-05 0:35 ` Ryan Chen
2025-10-24 7:56 ` Geert Uytterhoeven
2025-10-25 3:15 ` Ryan Chen
2025-10-22 7:05 ` [PATCH v6 5/6] arm64: dts: aspeed: Add AST2700 Evaluation Board Ryan Chen
2025-10-22 7:05 ` [PATCH v6 6/6] arm64: configs: Update defconfig for AST2700 platform support Ryan Chen
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