From: Andrew Lunn <andrew@lunn.ch>
To: Ryan Chen <ryan_chen@aspeedtech.com>
Cc: "Arnd Bergmann" <arnd@arndb.de>, BMC-SW <BMC-SW@aspeedtech.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Joel Stanley" <joel@jms.id.au>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Jeremy Kerr" <jk@codeconstruct.com.au>,
"Lee Jones" <lee@kernel.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@oss.qualcomm.com>,
"Geert Uytterhoeven" <geert@linux-m68k.org>,
"Nishanth Menon" <nm@ti.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Taniya Das" <quic_tdas@quicinc.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Kuninori Morimoto" <kuninori.morimoto.gx@renesas.com>,
"Eric Biggers" <ebiggers@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree
Date: Fri, 24 Oct 2025 14:28:26 +0200 [thread overview]
Message-ID: <71df9bdf-53b2-45e2-a9e3-5b00a556f957@lunn.ch> (raw)
In-Reply-To: <TY2PPF5CB9A1BE6CF8336D211641A18E2DEF2F1A@TY2PPF5CB9A1BE6.apcprd06.prod.outlook.com>
> > >> This probably needs some explanation: why are there two 'soc@...'
> > >> devices? Is this literally two chips in the system, or are you
> > >> describing two buses inside of the same SoC?
> > >
> > > The AST2700 is two soc connection with a property bus.
> > > Sharing some decode registers. Each have it own ahb bus.
> >
> > I don't understand your explanation,
>
> Let me clarify more clearly:
> The AST2700 is a dual-SoC architecture, consisting of two interconnected SoCs,
> referred to as SoC0 and SoC1. Each SoC has its own clock/reset domains.
> They are connected through an internal "property bus",
> which is Aspeed's internal interconnect providing shared
> address decoding and communication between the two SoCs.
By SoC are you just referring to peripherals? Or are there two sets of
CPUs as well?
If it is just peripherals, this has been done before by Marvell.
See armada-cp11x.dtsi. Marvell calls it a CP, they are identical, so
there is one description of it, which then gets included twice.
Andrew
next prev parent reply other threads:[~2025-10-24 12:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 7:05 [PATCH v6 0/6] Introduce ASPEED AST2700 BMC SoC Ryan Chen
2025-10-22 7:05 ` [PATCH v6 1/6] dt-bindings: arm: aspeed: Add AST2700 board compatible Ryan Chen
2025-10-22 7:05 ` [PATCH v6 2/6] arm64: Kconfig: Add Aspeed SoC family (ast27XX) Kconfig support Ryan Chen
2025-10-22 7:05 ` [PATCH v6 3/6] dt-bindings: mfd: aspeed,ast2x00-scu: allow #size-cells range Ryan Chen
2025-10-22 8:07 ` Krzysztof Kozlowski
2025-10-22 8:08 ` Krzysztof Kozlowski
2025-10-22 8:28 ` Ryan Chen
2025-10-22 7:05 ` [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Ryan Chen
2025-10-22 21:29 ` Arnd Bergmann
2025-10-23 7:37 ` Ryan Chen
2025-10-23 18:28 ` Andrew Lunn
2025-10-23 20:11 ` Arnd Bergmann
2025-10-24 3:54 ` Ryan Chen
2025-10-24 7:02 ` Arnd Bergmann
2025-10-24 12:28 ` Andrew Lunn [this message]
2025-10-25 3:08 ` Ryan Chen
2025-10-27 1:43 ` Andrew Lunn
2025-10-27 2:42 ` Ryan Chen
2025-10-27 12:01 ` Andrew Lunn
2025-10-27 12:53 ` Geert Uytterhoeven
2025-10-29 2:38 ` Ryan Chen
2025-10-29 9:52 ` Geert Uytterhoeven
2025-10-29 2:31 ` Ryan Chen
2025-10-29 7:26 ` Arnd Bergmann
2025-10-29 9:50 ` Geert Uytterhoeven
2025-10-30 2:30 ` Ryan Chen
2025-10-30 9:19 ` Arnd Bergmann
2025-11-05 0:35 ` Ryan Chen
2025-10-24 7:56 ` Geert Uytterhoeven
2025-10-25 3:15 ` Ryan Chen
2025-10-22 7:05 ` [PATCH v6 5/6] arm64: dts: aspeed: Add AST2700 Evaluation Board Ryan Chen
2025-10-22 7:05 ` [PATCH v6 6/6] arm64: configs: Update defconfig for AST2700 platform support Ryan Chen
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