From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: Alex Williamson <alex.williamson@redhat.com>, <vsethi@nvidia.com>,
<alwilliamson@nvidia.com>,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code
Date: Wed, 23 Sep 2026 16:40:05 -0500 [thread overview]
Message-ID: <6dc03976-faa8-49cb-9b74-680e957f2f9e@amd.com> (raw)
In-Reply-To: <20260922083924.2451158-7-smadhavan@nvidia.com>
On 9/22/2026 3:39 AM, Srirangan Madhavan wrote:
> PCI can be built in while CXL_BUS is modular, so PCI reset code cannot
> depend on helpers provided by the cxl_core module.
>
> Build the HDM resource helpers under CONFIG_CXL_RESET and restrict their
> exports to cxl_core.
>
I think you should squash this patch into 3/15. Having this earlier does two things:
1) it makes it more clear why you're moving everything earlier in the set, and 2)
bisects across the pass 3 patches will all result in the same configuration.
An alternative option would be to refactor the preceding 3 patches in-place and then
move all of the helpers to this file in this patch, either would work.
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
> drivers/cxl/Kconfig | 4 ++++
> drivers/cxl/core/Makefile | 2 +-
> drivers/cxl/core/resource.c | 4 ++++
> tools/testing/cxl/Kbuild | 1 -
> 4 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index 80aeb0d556bd..0cd704670735 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -6,6 +6,7 @@ menuconfig CXL_BUS
> select FW_UPLOAD
> select PCI_DOE
> select FIRMWARE_TABLE
> + select CXL_RESET
> select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS
> select FWCTL if CXL_FEATURES
> help
> @@ -244,3 +245,6 @@ config CXL_ATL
> depends on ACPI_PRMT && AMD_NB
>
> endif
> +
> +config CXL_RESET
> + bool
> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
> index 57995777af0d..30470799e059 100644
> --- a/drivers/cxl/core/Makefile
> +++ b/drivers/cxl/core/Makefile
> @@ -1,12 +1,12 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_CXL_BUS) += cxl_core.o
> +obj-$(CONFIG_CXL_RESET) += resource.o
This file should probably be called reset.c instead of resource.c to match the
Kconfig functionality.
> obj-$(CONFIG_CXL_SUSPEND) += suspend.o
>
> ccflags-y += -I$(srctree)/drivers/cxl
> CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src)
>
> cxl_core-y := port.o
> -cxl_core-y += resource.o
> cxl_core-y += pmem.o
> cxl_core-y += regs.o
> cxl_core-y += memdev.o
> diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
> index ea0d855e5549..1b4742622054 100644
> --- a/drivers/cxl/core/resource.c
> +++ b/drivers/cxl/core/resource.c
> @@ -3,6 +3,7 @@
> #include <linux/delay.h>
> #include <linux/bug.h>
> #include <linux/errno.h>
> +#include <linux/export.h>
> #include <linux/kernel.h>
>
> #include "cxl.h"
> @@ -12,6 +13,7 @@ struct cxl_rwsem cxl_rwsem = {
> .region = __RWSEM_INITIALIZER(cxl_rwsem.region),
> .dpa = __RWSEM_INITIALIZER(cxl_rwsem.dpa),
> };
> +EXPORT_SYMBOL_FOR_MODULES(cxl_rwsem, "cxl_core");
>
> static void cxld_set_interleave(struct cxl_decoder_config *config, u32 *ctrl)
> {
> @@ -100,8 +102,10 @@ void cxl_commit_start(void __iomem *hdm, struct cxl_decoder_settings *settings)
> lockdep_assert_held(&cxl_rwsem.dpa);
> setup_hw_decoder(hdm, settings);
> }
> +EXPORT_SYMBOL_FOR_MODULES(cxl_commit_start, "cxl_core");
>
> int cxl_commit_wait(void __iomem *hdm, struct cxl_decoder_settings *settings)
> {
> return cxld_await_commit(hdm, settings->config.id);
> }
> +EXPORT_SYMBOL_FOR_MODULES(cxl_commit_wait, "cxl_core");
> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
> index 6c09932587ce..2be1df80fcc9 100644
> --- a/tools/testing/cxl/Kbuild
> +++ b/tools/testing/cxl/Kbuild
> @@ -60,7 +60,6 @@ cxl_core-y += $(CXL_CORE_SRC)/memdev.o
> cxl_core-y += $(CXL_CORE_SRC)/mbox.o
> cxl_core-y += $(CXL_CORE_SRC)/pci.o
> cxl_core-y += $(CXL_CORE_SRC)/hdm.o
> -cxl_core-y += $(CXL_CORE_SRC)/resource.o
If you squash this patch you also don't need to bother adding/removing this.
> cxl_core-y += $(CXL_CORE_SRC)/pmu.o
> cxl_core-y += $(CXL_CORE_SRC)/cdat.o
> cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
next prev parent reply other threads:[~2026-09-23 21:40 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-24 1:16 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:21 ` Jonathan Cameron
2026-09-24 1:22 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-24 1:29 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-24 1:31 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:35 ` Jonathan Cameron
2026-09-24 2:45 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin [this message]
2026-09-24 2:49 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-24 3:05 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 3:08 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 3:36 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-22 8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-22 8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-23 21:41 ` Cheatham, Benjamin
2026-09-22 8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-24 3:50 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
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