mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Jonathan Cameron <jic23@kernel.org>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v13 07/15] cxl: Share HDM decoder register unpacking
Date: Thu, 24 Sep 2026 04:05:34 +0100	[thread overview]
Message-ID: <20260924040534.4eae3107@jic23-hlaptop> (raw)
In-Reply-To: <20260922083924.2451158-8-smadhavan@nvidia.com>

On Tue, 22 Sep 2026 08:39:16 +0000
Srirangan Madhavan <smadhavan@nvidia.com> wrote:

> Factor HDM register parsing into cxl_hdm_unpack_decoder(). Validate local
> values before publishing complete settings, including committed, locked,
> and target-or-skip state.
> 
> Pass endpoint skip state to the DPA reservation helper instead of
> updating live endpoint state, preserving its ownership.
> 
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>

A few little things inline as slightly more seems to change
in here than I'd immediately expect.

> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index b3ddc02df65e..98268e8e15b2 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -932,8 +932,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>  			    u64 *dpa_base, struct cxl_endpoint_dvsec_info *info)
>  {
>  	struct cxl_endpoint_decoder *cxled = NULL;
> -	u64 size, base, skip, dpa_size, lo, hi;
> -	bool committed;
> +	struct cxl_decoder_settings settings;
> +	u64 size, base, skip, dpa_size, lo, hi, target_or_skip_reg_val;
>  	u32 remainder;
>  	int i, rc;
>  	u32 ctrl;
> @@ -953,35 +953,34 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>  	lo = readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which));
>  	hi = readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(which));
>  	size = (hi << 32) + lo;
> -	committed = !!(ctrl & CXL_HDM_DECODER0_CTRL_COMMITTED);
> +	lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
> +	hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));
> +	target_or_skip_reg_val = (hi << 32) + lo;
> +	rc = cxl_hdm_unpack_decoder(&settings, which, ctrl, base, size,
> +				    target_or_skip_reg_val);
> +	if (rc) {
> +		dev_warn(&port->dev,
> +			 "decoder%d.%d: Invalid decoder configuration (ctrl: %#x): %d\n",
> +			 port->id, cxld->id, ctrl, rc);
> +		return rc;
> +	}
> +
>  	cxld->commit = cxl_decoder_commit;
>  	cxld->reset = cxl_decoder_reset;
> -
> -	if (!committed)
> -		size = 0;
> -	if (base == U64_MAX || size == U64_MAX) {
> -		dev_warn(&port->dev, "decoder%d.%d: Invalid resource range\n",
> -			 port->id, cxld->id);
> -		return -ENXIO;
> -	}
> +	cxld->config = settings.config;
> +	size = range_len(&cxld->hpa_range);
>  
>  	if (info)
>  		cxled = to_cxl_endpoint_decoder(&cxld->dev);
> -	cxld->hpa_range = (struct range) {
> -		.start = base,
> -		.end = base + size - 1,
> -	};
> +	if (!cxled && cxld->interleave_ways > 8) {

Why does this check make sense now when we didn't have it before
(that I can find anyway)?  If it isn't tightly coupled to this
patch and instead is providing some extra checks that are worthwhile
I'd break it out as a separate patch where that usecase can be
well described.

> +		dev_warn(&port->dev,
> +			 "decoder%d.%d: Invalid target count: %d\n",
> +			 port->id, cxld->id, cxld->interleave_ways);
> +		return -ENXIO;
> +	}
>  
>  	/* decoders are enabled if committed */
> -	if (committed) {
> -		cxld->flags |= CXL_DECODER_F_ENABLE;
> -		if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> -			cxld->flags |= CXL_DECODER_F_LOCK;
> -		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
> -			cxld->target_type = CXL_DECODER_HOSTONLYMEM;
> -		else
> -			cxld->target_type = CXL_DECODER_DEVMEM;
> -
> +	if (cxld->flags & CXL_DECODER_F_ENABLE) {

> diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
> index 1b4742622054..7eea2bc38d94 100644
> --- a/drivers/cxl/core/resource.c
> +++ b/drivers/cxl/core/resource.c
> @@ -109,3 +109,58 @@ int cxl_commit_wait(void __iomem *hdm, struct cxl_decoder_settings *settings)
>  	return cxld_await_commit(hdm, settings->config.id);
>  }
>  EXPORT_SYMBOL_FOR_MODULES(cxl_commit_wait, "cxl_core");
> +
> +int cxl_hdm_unpack_decoder(struct cxl_decoder_settings *settings, int id,
> +			   u32 ctrl, u64 base, u64 size,
> +			   u64 target_or_skip_reg_val)
> +{
> +	bool committed = FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl);
> +	enum cxl_decoder_type target_type;
> +	int interleave_granularity;
> +	int interleave_ways;
> +	unsigned long flags = 0;
> +	struct range hpa_range;
> +	int rc;
> +
> +	if (!committed)
> +		size = 0;
> +	if (base == U64_MAX || size == U64_MAX ||
> +	    (size && base > U64_MAX - (size - 1)))
> +		return -ENXIO;

This second block looks like new defences which is fine but I'm not sure
it makes sense in here.  Also given we are just checking overflow
doesn't happen maybe use check_add_overflow(). Saves us thinking too
much the maths.
 
> +
> +	hpa_range = (struct range) {
> +		.start = base,
> +		.end = base + size - 1,
> +	};
> +	target_type = FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) ?
> +		      CXL_DECODER_HOSTONLYMEM : CXL_DECODER_DEVMEM;

Maybe stick to the if / else of the original? I think that is more readable for
an extra couple of lines.
Also blank line here to give visual separation before the conditional that
follows.

It's a functional change to move the target_type selection out of the
committed check. I'd like to see some discussion of why that is fine to
do which probably means a separate little patch that has that description
on its own.

> +	if (committed) {
> +		flags |= CXL_DECODER_F_ENABLE;
> +		if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
> +			flags |= CXL_DECODER_F_LOCK;
> +	}
Thanks

Jonathan



  reply	other threads:[~2026-09-24  3:05 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22  8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-24  1:16   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:21     ` Jonathan Cameron
2026-09-24  1:22   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-24  1:29   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-24  1:31   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:35     ` Jonathan Cameron
2026-09-24  2:45   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  2:49     ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-24  3:05   ` Jonathan Cameron [this message]
2026-09-22  8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  3:08   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  3:36   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-23 21:41   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-24  3:50   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260924040534.4eae3107@jic23-hlaptop \
    --to=jic23@kernel.org \
    --cc=alex.williamson@redhat.com \
    --cc=alison.schofield@intel.com \
    --cc=alwilliamson@nvidia.com \
    --cc=bhelgaas@google.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=icheng@nvidia.com \
    --cc=ira.weiny@intel.com \
    --cc=jan@nvidia.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=mhonap@nvidia.com \
    --cc=skancherla@nvidia.com \
    --cc=smadhavan@nvidia.com \
    --cc=vaslot@nvidia.com \
    --cc=vishal.l.verma@intel.com \
    --cc=vsethi@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®