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From: Jonathan Cameron <jic23@kernel.org>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings
Date: Thu, 24 Sep 2026 03:45:31 +0100	[thread overview]
Message-ID: <20260924034531.0210cafd@jic23-hlaptop> (raw)
In-Reply-To: <20260922083924.2451158-6-smadhavan@nvidia.com>

On Tue, 22 Sep 2026 08:39:14 +0000
Srirangan Madhavan <smadhavan@nvidia.com> wrote:

> Represent HDM programming state with struct cxl_decoder_settings and pass
> it to the commit helpers. Keep endpoint skip and switch targets at their
> call sites, place flags with the programming state, and leave runtime
> region ownership outside the snapshot.
> 
> Separate commit initiation from completion waiting so reset restoration
> can reuse register programming without changing normal DPA-lock policy.
> 
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Hi Srirangan,

I'm not sure if others will agree, but my inclination here
would not be to use the struct_group_tagged machine because
of the structure then being embedded in two places.

I'd just define the structure independently and pay the price
in churn to access the version in cxl_decoder.  The point being
to say 'these are the bits of cxl_decoder that we need
to store for reset purposes'.

Jonathan

> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 69941f7fdb76..1acdf537e4e9 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -42,8 +42,8 @@ enum cxl_decoder_type {
>   * @interleave_ways: number of cxl_dports in this decode
>   * @interleave_granularity: data stride per dport
>   * @target_type: accelerator vs expander (type2 vs type3) selector
> - * @region: currently assigned region for this decoder
>   * @flags: memory type capabilities and locking
> + * @region: currently assigned region for this decoder
>   * @target_map: cached copy of hardware port-id list, available at init
>   *              before all @dport objects have been instantiated. While
>   *              dport id is 8bit, CFMWS interleave targets are 32bits.
> @@ -52,18 +52,31 @@ enum cxl_decoder_type {
>  */
>  struct cxl_decoder {
>  	struct device dev;
> -	int id;
> -	struct range hpa_range;
> -	int interleave_ways;
> -	int interleave_granularity;
> -	enum cxl_decoder_type target_type;
> +
> +	struct_group_tagged(cxl_decoder_config, config,

Whilst strictly speaking correct, to me struct_group_tagged()
should only really be used when there is only one place that
the structure appears.  Otherwise it is just a bit obscure
to read.  It does give us the option of accessing the elements
in here without the extra jump, but I'm not sure that is
a good idea in this case.  So I'd just make this a normal
structure.  After all what is special about it being
defined here that isn't equally true of the cxl_decoder_settings
structure below?

> +		int id;
> +		struct range hpa_range;
> +		int interleave_ways;
> +		int interleave_granularity;
> +		enum cxl_decoder_type target_type;
> +		unsigned long flags;
> +	);
>  	struct cxl_region *region;
> -	unsigned long flags;
>  	u32 target_map[CXL_DECODER_MAX_INTERLEAVE];
>  	int (*commit)(struct cxl_decoder *cxld);
>  	void (*reset)(struct cxl_decoder *cxld);
>  };
>  
> +/**
> + * struct cxl_decoder_settings - CXL HDM decoder programming snapshot
> + * @config: common decoder configuration
> + * @target_or_skip_reg_val: switch target list or endpoint skip register value
> + */
> +struct cxl_decoder_settings {
> +	struct cxl_decoder_config config;
> +	u64 target_or_skip_reg_val;
> +};
> +
>  /*
>   * Using struct_group() allows for per register-block-type helper routines,
>   * without requiring block-type agnostic code to include the prefix.


  parent reply	other threads:[~2026-09-24  2:45 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22  8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-24  1:16   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:21     ` Jonathan Cameron
2026-09-24  1:22   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-24  1:29   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-24  1:31   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-23 21:39   ` Cheatham, Benjamin
2026-09-24  1:35     ` Jonathan Cameron
2026-09-24  2:45   ` Jonathan Cameron [this message]
2026-09-22  8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  2:49     ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-24  3:05   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  3:08   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-24  3:36   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-23 21:40   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-23 21:41   ` Cheatham, Benjamin
2026-09-22  8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-24  3:50   ` Jonathan Cameron
2026-09-22  8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22  8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan

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