[PATCH v3 0/3] Decouple max_pclk check from constant display feats

[PATCH v3 0/3] Decouple max_pclk check from constant display feats

[Jayesh Choudhary]

In an effort to make the existing compatibles more usable, we are
removing the max_pclk_khz form dispc_features structure and doing the
correspondig checks using "curr_max_pclk[]".

Changes are fully backwards compatible.

After integration of OLDI support[0], we need additional patches in
oldi to identify the VP that has OLDI. We have to do this since
OLDI driver owns the VP clock (its serial clock) and we cannot perform
clock operations on those VP clock from tidss driver. This issue was
also reported upstream when DSI fixes[1] had some clock related calls
in tidss driver. When "clk_round_rate()" is called, ideally it should
have gone to "sci_clk_determine_rate()" to query DM but it doesn't since
clock is owned by OLDI not tidss.

So add a member is_oldi_vp[] in tidss_device structure to identify this
and avoid performing clock operations for VP if it has OLDI panel.
For the same checks in OLDI driver, atomic_check() hook is added to its
bridge_funcs.
In the atomic_check() chain, first the bridge_atomic_check() is called
and then crtc_atomic_check() is called. So mode clock is first checked
in oldi driver and then skipped in tidss driver.

Had the tidss_oldi structure been exposed to tidss_dispc.c, we could
have directly checked VP type in dispc but since the structure is defined
in tidss_oldi.c , we have to add additional member to tidss_device
structure.

[0]: https://lore.kernel.org/all/20250528122544.817829-1-aradhya.bhatia@linux.dev/
[1]: https://lore.kernel.org/all/DA6TT575Z82D.3MPK8HG5GRL8U@kernel.org/

Changelog v2->v3:
- Add changes for OLDI
- Rename max_pclk as it is misleading
- Change commit message to make it more appropriate
- Drop unnecessary zero initialization

v2 patch link:
https://lore.kernel.org/all/20250618100509.20386-1-j-choudhary@ti.com/

Changelog v1->v2:
- Rebase it on linux-next after OLDI support series as all of its
  patches are reviewed and tested and it touches one of the functions
  used.
  
v1 patch link:
https://lore.kernel.org/all/20250618075804.139844-1-j-choudhary@ti.com/

Jayesh Choudhary (3):
  drm/tidss: oldi: Add property to identify OLDI supported VP
  drm/tidss: Remove max_pclk_khz from tidss display features
  drm/tidss: oldi: Add atomic_check hook for oldi bridge

 drivers/gpu/drm/tidss/tidss_dispc.c | 77 +++++++++++------------------
 drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
 drivers/gpu/drm/tidss/tidss_drv.h   |  4 ++
 drivers/gpu/drm/tidss/tidss_oldi.c  | 26 ++++++++++
 4 files changed, 59 insertions(+), 49 deletions(-)

-- 
2.34.1

[PATCH v3 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Jayesh Choudhary]

TIDSS should know which VP has OLDI output to avoid calling clock
functions for that VP as those are controlled by oldi driver. Add a
property "is_oldi_vp" to "tidss_device" structure for that. Mark it
'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
 drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
index 0ae24f645582..82beaaceadb3 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.h
+++ b/drivers/gpu/drm/tidss/tidss_drv.h
@@ -24,6 +24,8 @@ struct tidss_device {
 
 	const struct dispc_features *feat;
 	struct dispc_device *dispc;
+	bool is_oldi_vp[TIDSS_MAX_PORTS];
+
 
 	unsigned int num_crtcs;
 	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
index b0f99656e87e..63e07c8edeaa 100644
--- a/drivers/gpu/drm/tidss/tidss_oldi.c
+++ b/drivers/gpu/drm/tidss/tidss_oldi.c
@@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
 	for (int i = 0; i < tidss->num_oldis; i++) {
 		if (tidss->oldis[i]) {
 			drm_bridge_remove(&tidss->oldis[i]->bridge);
+			tidss->is_oldi_vp[tidss->oldis[i]->parent_vp] = false;
 			tidss->oldis[i] = NULL;
 		}
 	}
@@ -579,6 +580,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
 		oldi->bridge.timings = &default_tidss_oldi_timings;
 
 		tidss->oldis[tidss->num_oldis++] = oldi;
+		tidss->is_oldi_vp[oldi->parent_vp] = true;
 		oldi->tidss = tidss;
 
 		drm_bridge_add(&oldi->bridge);
-- 
2.34.1

Re: [PATCH v3 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Devarsh Thakkar]

On 01/07/25 15:25, Jayesh Choudhary wrote:
> TIDSS should know which VP has OLDI output to avoid calling clock
> functions for that VP as those are controlled by oldi driver. Add a
> property "is_oldi_vp" to "tidss_device" structure for that. Mark it
> 'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().
> 
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>

Reviewed-by: Devarsh Thakkar <devarsht@ti.com>

Regards
Devarsh
> ---
>   drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
>   drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
> index 0ae24f645582..82beaaceadb3 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.h
> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
> @@ -24,6 +24,8 @@ struct tidss_device {
>   
>   	const struct dispc_features *feat;
>   	struct dispc_device *dispc;
> +	bool is_oldi_vp[TIDSS_MAX_PORTS];
> +
>   
>   	unsigned int num_crtcs;
>   	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
> index b0f99656e87e..63e07c8edeaa 100644
> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> @@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
>   	for (int i = 0; i < tidss->num_oldis; i++) {
>   		if (tidss->oldis[i]) {
>   			drm_bridge_remove(&tidss->oldis[i]->bridge);
> +			tidss->is_oldi_vp[tidss->oldis[i]->parent_vp] = false;
>   			tidss->oldis[i] = NULL;
>   		}
>   	}
> @@ -579,6 +580,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
>   		oldi->bridge.timings = &default_tidss_oldi_timings;
>   
>   		tidss->oldis[tidss->num_oldis++] = oldi;
> +		tidss->is_oldi_vp[oldi->parent_vp] = true;
>   		oldi->tidss = tidss;
>   
>   		drm_bridge_add(&oldi->bridge);

[PATCH v3 2/3] drm/tidss: Remove max_pclk_khz from tidss display features

[Jayesh Choudhary]

TIDSS hardware by itself does not have variable max_pclk for each VP.
The maximum pixel clock is determined by the limiting factor between
the functional clock and the PLL.

The limitation that has been modeled till now comes from the clock
(PLL can only be programmed to a particular max value). Instead of
putting it as a constant field in dispc_features, we can query the
DM to see if requested clock can be set or not and use it in
"mode_valid()".

Replace constant "max_pclk_khz" in dispc_features with "curr_max_pclk"
in tidss_device structure which would be modified in runtime.
In mode_valid() call, check if a best frequency match for mode clock
can be found or not using "clk_round_rate()". Based on that, propagate
"cur_max_pclk" and query DM again only if the requested mode clock
is greater than cur_max_pclk. (As the preferred display mode is usually
the max resolution, driver ends up checking the highest clock the first
time itself which is used in subsequent checks)

Since TIDSS display controller provides clock tolerance of 5%, we use
this while checking the curr_max_pclk. Also, move up "dispc_pclk_diff()"
before it is called.

This will make the existing compatibles reusable.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 drivers/gpu/drm/tidss/tidss_dispc.c | 77 +++++++++++------------------
 drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
 drivers/gpu/drm/tidss/tidss_drv.h   |  2 +
 3 files changed, 31 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 3f6cff2ab1b2..fb59a6a0f86a 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -58,10 +58,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 const struct dispc_features dispc_k2g_feats = {
 	.min_pclk_khz = 4375,
 
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 150000,
-	},
-
 	/*
 	 * XXX According TRM the RGB input buffer width up to 2560 should
 	 *     work on 3 taps, but in practice it only works up to 1280.
@@ -144,11 +140,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 };
 
 const struct dispc_features dispc_am65x_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-		[DISPC_VP_OLDI_AM65X] = 165000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -244,11 +235,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 };
 
 const struct dispc_features dispc_j721e_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 170000,
-		[DISPC_VP_INTERNAL] = 600000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 2048,
 		.in_width_max_3tap_rgb = 4096,
@@ -315,11 +301,6 @@ const struct dispc_features dispc_j721e_feats = {
 };
 
 const struct dispc_features dispc_am625_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-		[DISPC_VP_INTERNAL] = 170000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -376,15 +357,6 @@ const struct dispc_features dispc_am625_feats = {
 };
 
 const struct dispc_features dispc_am62a7_feats = {
-	/*
-	 * if the code reaches dispc_mode_valid with VP1,
-	 * it should return MODE_BAD.
-	 */
-	.max_pclk_khz = {
-		[DISPC_VP_TIED_OFF] = 0,
-		[DISPC_VP_DPI] = 165000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -441,10 +413,6 @@ const struct dispc_features dispc_am62a7_feats = {
 };
 
 const struct dispc_features dispc_am62l_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-	},
-
 	.subrev = DISPC_AM62L,
 
 	.common = "common",
@@ -1347,25 +1315,49 @@ static void dispc_vp_set_default_color(struct dispc_device *dispc,
 			DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
 }
 
+/*
+ * Calculate the percentage difference between the requested pixel clock rate
+ * and the effective rate resulting from calculating the clock divider value.
+ */
+unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
+{
+	int r = rate / 100, rr = real_rate / 100;
+
+	return (unsigned int)(abs(((rr - r) * 100) / r));
+}
+
+static int check_pixel_clock(struct dispc_device *dispc,
+			     u32 hw_videoport, unsigned long clock)
+{
+	if (clock > dispc->tidss->curr_max_pclk[hw_videoport] &&
+	    !dispc->tidss->is_oldi_vp[hw_videoport]) {
+		unsigned long round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock);
+
+		if (dispc_pclk_diff(clock, round_clock) > 5)
+			return -EINVAL;
+
+		dispc->tidss->curr_max_pclk[hw_videoport] = round_clock;
+	}
+
+	return 0;
+}
+
 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
 					 u32 hw_videoport,
 					 const struct drm_display_mode *mode)
 {
 	u32 hsw, hfp, hbp, vsw, vfp, vbp;
 	enum dispc_vp_bus_type bus_type;
-	int max_pclk;
 
 	bus_type = dispc->feat->vp_bus_type[hw_videoport];
 
-	max_pclk = dispc->feat->max_pclk_khz[bus_type];
-
-	if (WARN_ON(max_pclk == 0))
+	if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
 		return MODE_BAD;
 
 	if (mode->clock < dispc->feat->min_pclk_khz)
 		return MODE_CLOCK_LOW;
 
-	if (mode->clock > max_pclk)
+	if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
 		return MODE_CLOCK_HIGH;
 
 	if (mode->hdisplay > 4096)
@@ -1437,17 +1429,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
 	clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
 }
 
-/*
- * Calculate the percentage difference between the requested pixel clock rate
- * and the effective rate resulting from calculating the clock divider value.
- */
-unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
-{
-	int r = rate / 100, rr = real_rate / 100;
-
-	return (unsigned int)(abs(((rr - r) * 100) / r));
-}
-
 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
 			  unsigned long rate)
 {
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index 60c1b400eb89..fbfe6e304ac8 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
 
 struct dispc_features {
 	int min_pclk_khz;
-	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
 
 	struct dispc_features_scaling scaling;
 
diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
index 82beaaceadb3..e89c38a386f7 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.h
+++ b/drivers/gpu/drm/tidss/tidss_drv.h
@@ -25,6 +25,8 @@ struct tidss_device {
 	const struct dispc_features *feat;
 	struct dispc_device *dispc;
 	bool is_oldi_vp[TIDSS_MAX_PORTS];
+	/* stores max supported pixel clock requested during checking modes */
+	unsigned long curr_max_pclk[TIDSS_MAX_PORTS];
 
 
 	unsigned int num_crtcs;
-- 
2.34.1

Re: [PATCH v3 2/3] drm/tidss: Remove max_pclk_khz from tidss display features

[Devarsh Thakkar]

Hi Jayesh,

On 01/07/25 15:25, Jayesh Choudhary wrote:
> TIDSS hardware by itself does not have variable max_pclk for each VP.
> The maximum pixel clock is determined by the limiting factor between
> the functional clock and the PLL

and the pixel clock
.
> 
> The limitation that has been modeled till now comes from the clock
> (PLL can only be programmed to a particular max value). Instead of
> putting it as a constant field in dispc_features, we can query the
> DM to see if requested clock can be set or not and use it in
> "mode_valid()".
> 
> Replace constant "max_pclk_khz" in dispc_features with "curr_max_pclk"
> in tidss_device structure which would be modified in runtime.
> In mode_valid() call, check if a best frequency match for mode clock
> can be found or not using "clk_round_rate()". Based on that, propagate
> "cur_max_pclk" and query DM again only if the requested mode clock
> is greater than cur_max_pclk. (As the preferred display mode is usually
> the max resolution, driver ends up checking the highest clock the first
> time itself which is used in subsequent checks)
> 
> Since TIDSS display controller provides clock tolerance of 5%, we use
> this while checking the curr_max_pclk. Also, move up "dispc_pclk_diff()"
> before it is called.
> 
> This will make the existing compatibles reusable

reusable if DSS features are same across two SoCs and only difference 
being the pixel clock.

> 
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
>   drivers/gpu/drm/tidss/tidss_dispc.c | 77 +++++++++++------------------
>   drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
>   drivers/gpu/drm/tidss/tidss_drv.h   |  2 +
>   3 files changed, 31 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 3f6cff2ab1b2..fb59a6a0f86a 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -58,10 +58,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>   const struct dispc_features dispc_k2g_feats = {
>   	.min_pclk_khz = 4375,
>   
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 150000,
> -	},
> -
>   	/*
>   	 * XXX According TRM the RGB input buffer width up to 2560 should
>   	 *     work on 3 taps, but in practice it only works up to 1280.
> @@ -144,11 +140,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>   };
>   
>   const struct dispc_features dispc_am65x_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_OLDI_AM65X] = 165000,
> -	},
> -
>   	.scaling = {
>   		.in_width_max_5tap_rgb = 1280,
>   		.in_width_max_3tap_rgb = 2560,
> @@ -244,11 +235,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>   };
>   
>   const struct dispc_features dispc_j721e_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 170000,
> -		[DISPC_VP_INTERNAL] = 600000,
> -	},
> -
>   	.scaling = {
>   		.in_width_max_5tap_rgb = 2048,
>   		.in_width_max_3tap_rgb = 4096,
> @@ -315,11 +301,6 @@ const struct dispc_features dispc_j721e_feats = {
>   };
>   
>   const struct dispc_features dispc_am625_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_INTERNAL] = 170000,
> -	},
> -
>   	.scaling = {
>   		.in_width_max_5tap_rgb = 1280,
>   		.in_width_max_3tap_rgb = 2560,
> @@ -376,15 +357,6 @@ const struct dispc_features dispc_am625_feats = {
>   };
>   
>   const struct dispc_features dispc_am62a7_feats = {
> -	/*
> -	 * if the code reaches dispc_mode_valid with VP1,
> -	 * it should return MODE_BAD.
> -	 */
> -	.max_pclk_khz = {
> -		[DISPC_VP_TIED_OFF] = 0,
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>   	.scaling = {
>   		.in_width_max_5tap_rgb = 1280,
>   		.in_width_max_3tap_rgb = 2560,
> @@ -441,10 +413,6 @@ const struct dispc_features dispc_am62a7_feats = {
>   };
>   
>   const struct dispc_features dispc_am62l_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>   	.subrev = DISPC_AM62L,
>   
>   	.common = "common",
> @@ -1347,25 +1315,49 @@ static void dispc_vp_set_default_color(struct dispc_device *dispc,
>   			DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
>   }
>   
> +/*
> + * Calculate the percentage difference between the requested pixel clock rate
> + * and the effective rate resulting from calculating the clock divider value.
> + */
> +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> +{
> +	int r = rate / 100, rr = real_rate / 100;
> +
> +	return (unsigned int)(abs(((rr - r) * 100) / r));
> +}
> +
> +static int check_pixel_clock(struct dispc_device *dispc,
> +			     u32 hw_videoport, unsigned long clock)
> +{
> +	if (clock > dispc->tidss->curr_max_pclk[hw_videoport] &&
> +	    !dispc->tidss->is_oldi_vp[hw_videoport]) {
> +		unsigned long round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock);
> +
> +		if (dispc_pclk_diff(clock, round_clock) > 5)
> +			return -EINVAL;
> +
> +		dispc->tidss->curr_max_pclk[hw_videoport] = round_clock;
> +	}
> +
> +	return 0;
> +}
> +
>   enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
>   					 u32 hw_videoport,
>   					 const struct drm_display_mode *mode)
>   {
>   	u32 hsw, hfp, hbp, vsw, vfp, vbp;
>   	enum dispc_vp_bus_type bus_type;
> -	int max_pclk;
>   
>   	bus_type = dispc->feat->vp_bus_type[hw_videoport];
>   
> -	max_pclk = dispc->feat->max_pclk_khz[bus_type];
> -
> -	if (WARN_ON(max_pclk == 0))
> +	if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
>   		return MODE_BAD;
>   
>   	if (mode->clock < dispc->feat->min_pclk_khz)
>   		return MODE_CLOCK_LOW;
>   
> -	if (mode->clock > max_pclk)
> +	if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
>   		return MODE_CLOCK_HIGH;
>   
>   	if (mode->hdisplay > 4096)
> @@ -1437,17 +1429,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
>   	clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
>   }
>   
> -/*
> - * Calculate the percentage difference between the requested pixel clock rate
> - * and the effective rate resulting from calculating the clock divider value.
> - */
> -unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> -{
> -	int r = rate / 100, rr = real_rate / 100;
> -
> -	return (unsigned int)(abs(((rr - r) * 100) / r));
> -}
> -
>   int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
>   			  unsigned long rate)
>   {
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
> index 60c1b400eb89..fbfe6e304ac8 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.h
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.h
> @@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
>   
>   struct dispc_features {
>   	int min_pclk_khz;
> -	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
>   
>   	struct dispc_features_scaling scaling;
>   
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
> index 82beaaceadb3..e89c38a386f7 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.h
> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
> @@ -25,6 +25,8 @@ struct tidss_device {
>   	const struct dispc_features *feat;
>   	struct dispc_device *dispc;
>   	bool is_oldi_vp[TIDSS_MAX_PORTS];
> +	/* stores max supported pixel clock requested during checking modes */

Stores highest pixel clock value found to be valid while checking 
supported modes for connected display

With suggested changes,
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>

Regards
Devarsh

> +	unsigned long curr_max_pclk[TIDSS_MAX_PORTS];
>   
>   
>   	unsigned int num_crtcs;

Re: [PATCH v3 2/3] drm/tidss: Remove max_pclk_khz from tidss display features

[Jayesh Choudhary]

Hello Devarsh,

On 01/07/25 18:42, Devarsh Thakkar wrote:
> Hi Jayesh,
> 
> On 01/07/25 15:25, Jayesh Choudhary wrote:
>> TIDSS hardware by itself does not have variable max_pclk for each VP.
>> The maximum pixel clock is determined by the limiting factor between
>> the functional clock and the PLL
> 
> and the pixel clock

PLL is the parent to that pixel clock so seemed implicit to me.
But will make it more clear.

> .
>>
>> The limitation that has been modeled till now comes from the clock
>> (PLL can only be programmed to a particular max value). Instead of
>> putting it as a constant field in dispc_features, we can query the
>> DM to see if requested clock can be set or not and use it in
>> "mode_valid()".
>>
>> Replace constant "max_pclk_khz" in dispc_features with "curr_max_pclk"
>> in tidss_device structure which would be modified in runtime.
>> In mode_valid() call, check if a best frequency match for mode clock
>> can be found or not using "clk_round_rate()". Based on that, propagate
>> "cur_max_pclk" and query DM again only if the requested mode clock
>> is greater than cur_max_pclk. (As the preferred display mode is usually
>> the max resolution, driver ends up checking the highest clock the first
>> time itself which is used in subsequent checks)
>>
>> Since TIDSS display controller provides clock tolerance of 5%, we use
>> this while checking the curr_max_pclk. Also, move up "dispc_pclk_diff()"
>> before it is called.
>>
>> This will make the existing compatibles reusable
> 
> reusable if DSS features are same across two SoCs and only difference 
> being the pixel clock.

Sure.

> 
>>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>>   drivers/gpu/drm/tidss/tidss_dispc.c | 77 +++++++++++------------------
>>   drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
>>   drivers/gpu/drm/tidss/tidss_drv.h   |  2 +
>>   3 files changed, 31 insertions(+), 49 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c 
>> b/drivers/gpu/drm/tidss/tidss_dispc.c
>> index 3f6cff2ab1b2..fb59a6a0f86a 100644
>> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
>> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
>> @@ -58,10 +58,6 @@ static const u16 
>> tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>>   const struct dispc_features dispc_k2g_feats = {
>>       .min_pclk_khz = 4375,
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_DPI] = 150000,
>> -    },
>> -
>>       /*
>>        * XXX According TRM the RGB input buffer width up to 2560 should
>>        *     work on 3 taps, but in practice it only works up to 1280.
>> @@ -144,11 +140,6 @@ static const u16 
>> tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>>   };
>>   const struct dispc_features dispc_am65x_feats = {
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_DPI] = 165000,
>> -        [DISPC_VP_OLDI_AM65X] = 165000,
>> -    },
>> -
>>       .scaling = {
>>           .in_width_max_5tap_rgb = 1280,
>>           .in_width_max_3tap_rgb = 2560,
>> @@ -244,11 +235,6 @@ static const u16 
>> tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>>   };
>>   const struct dispc_features dispc_j721e_feats = {
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_DPI] = 170000,
>> -        [DISPC_VP_INTERNAL] = 600000,
>> -    },
>> -
>>       .scaling = {
>>           .in_width_max_5tap_rgb = 2048,
>>           .in_width_max_3tap_rgb = 4096,
>> @@ -315,11 +301,6 @@ const struct dispc_features dispc_j721e_feats = {
>>   };
>>   const struct dispc_features dispc_am625_feats = {
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_DPI] = 165000,
>> -        [DISPC_VP_INTERNAL] = 170000,
>> -    },
>> -
>>       .scaling = {
>>           .in_width_max_5tap_rgb = 1280,
>>           .in_width_max_3tap_rgb = 2560,
>> @@ -376,15 +357,6 @@ const struct dispc_features dispc_am625_feats = {
>>   };
>>   const struct dispc_features dispc_am62a7_feats = {
>> -    /*
>> -     * if the code reaches dispc_mode_valid with VP1,
>> -     * it should return MODE_BAD.
>> -     */
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_TIED_OFF] = 0,
>> -        [DISPC_VP_DPI] = 165000,
>> -    },
>> -
>>       .scaling = {
>>           .in_width_max_5tap_rgb = 1280,
>>           .in_width_max_3tap_rgb = 2560,
>> @@ -441,10 +413,6 @@ const struct dispc_features dispc_am62a7_feats = {
>>   };
>>   const struct dispc_features dispc_am62l_feats = {
>> -    .max_pclk_khz = {
>> -        [DISPC_VP_DPI] = 165000,
>> -    },
>> -
>>       .subrev = DISPC_AM62L,
>>       .common = "common",
>> @@ -1347,25 +1315,49 @@ static void dispc_vp_set_default_color(struct 
>> dispc_device *dispc,
>>               DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
>>   }
>> +/*
>> + * Calculate the percentage difference between the requested pixel 
>> clock rate
>> + * and the effective rate resulting from calculating the clock 
>> divider value.
>> + */
>> +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long 
>> real_rate)
>> +{
>> +    int r = rate / 100, rr = real_rate / 100;
>> +
>> +    return (unsigned int)(abs(((rr - r) * 100) / r));
>> +}
>> +
>> +static int check_pixel_clock(struct dispc_device *dispc,
>> +                 u32 hw_videoport, unsigned long clock)
>> +{
>> +    if (clock > dispc->tidss->curr_max_pclk[hw_videoport] &&
>> +        !dispc->tidss->is_oldi_vp[hw_videoport]) {
>> +        unsigned long round_clock = 
>> clk_round_rate(dispc->vp_clk[hw_videoport], clock);
>> +
>> +        if (dispc_pclk_diff(clock, round_clock) > 5)
>> +            return -EINVAL;
>> +
>> +        dispc->tidss->curr_max_pclk[hw_videoport] = round_clock;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>>   enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
>>                        u32 hw_videoport,
>>                        const struct drm_display_mode *mode)
>>   {
>>       u32 hsw, hfp, hbp, vsw, vfp, vbp;
>>       enum dispc_vp_bus_type bus_type;
>> -    int max_pclk;
>>       bus_type = dispc->feat->vp_bus_type[hw_videoport];
>> -    max_pclk = dispc->feat->max_pclk_khz[bus_type];
>> -
>> -    if (WARN_ON(max_pclk == 0))
>> +    if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
>>           return MODE_BAD;
>>       if (mode->clock < dispc->feat->min_pclk_khz)
>>           return MODE_CLOCK_LOW;
>> -    if (mode->clock > max_pclk)
>> +    if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
>>           return MODE_CLOCK_HIGH;
>>       if (mode->hdisplay > 4096)
>> @@ -1437,17 +1429,6 @@ void dispc_vp_disable_clk(struct dispc_device 
>> *dispc, u32 hw_videoport)
>>       clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
>>   }
>> -/*
>> - * Calculate the percentage difference between the requested pixel 
>> clock rate
>> - * and the effective rate resulting from calculating the clock 
>> divider value.
>> - */
>> -unsigned int dispc_pclk_diff(unsigned long rate, unsigned long 
>> real_rate)
>> -{
>> -    int r = rate / 100, rr = real_rate / 100;
>> -
>> -    return (unsigned int)(abs(((rr - r) * 100) / r));
>> -}
>> -
>>   int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
>>                 unsigned long rate)
>>   {
>> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h 
>> b/drivers/gpu/drm/tidss/tidss_dispc.h
>> index 60c1b400eb89..fbfe6e304ac8 100644
>> --- a/drivers/gpu/drm/tidss/tidss_dispc.h
>> +++ b/drivers/gpu/drm/tidss/tidss_dispc.h
>> @@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
>>   struct dispc_features {
>>       int min_pclk_khz;
>> -    int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
>>       struct dispc_features_scaling scaling;
>> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h 
>> b/drivers/gpu/drm/tidss/tidss_drv.h
>> index 82beaaceadb3..e89c38a386f7 100644
>> --- a/drivers/gpu/drm/tidss/tidss_drv.h
>> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
>> @@ -25,6 +25,8 @@ struct tidss_device {
>>       const struct dispc_features *feat;
>>       struct dispc_device *dispc;
>>       bool is_oldi_vp[TIDSS_MAX_PORTS];
>> +    /* stores max supported pixel clock requested during checking 
>> modes */
> 
> Stores highest pixel clock value found to be valid while checking 
> supported modes for connected display

Will change in v4.

Thanks,
Jayesh

> 
> With suggested changes,
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> 
> Regards
> Devarsh
> 
>> +    unsigned long curr_max_pclk[TIDSS_MAX_PORTS];
>>       unsigned int num_crtcs;

[PATCH v3 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Jayesh Choudhary]

Since OLDI consumes DSS VP clock directly as serial clock, certain
checks cannot be performed in tidss driver which should be checked
in oldi driver. Add check for mode clock and set the curr_max_pclk
field for tidss in case the VP is OLDI.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
 drivers/gpu/drm/tidss/tidss_oldi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
index 63e07c8edeaa..a1f5fb39b32c 100644
--- a/drivers/gpu/drm/tidss/tidss_oldi.c
+++ b/drivers/gpu/drm/tidss/tidss_oldi.c
@@ -309,6 +309,29 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 	return input_fmts;
 }
 
+static int tidss_oldi_bridge_atomic_check(struct drm_bridge *bridge,
+					  struct drm_bridge_state *bridge_state,
+					  struct drm_crtc_state *crtc_state,
+					  struct drm_connector_state *conn_state)
+{
+	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
+	struct drm_display_mode *adjusted_mode;
+	unsigned long round_clock;
+
+	adjusted_mode = &crtc_state->adjusted_mode;
+
+	if (adjusted_mode->clock > oldi->tidss->curr_max_pclk[oldi->parent_vp]) {
+		round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
+
+		if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
+			return -EINVAL;
+
+		oldi->tidss->curr_max_pclk[oldi->parent_vp] = round_clock;
+	}
+
+	return 0;
+}
+
 static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
 	.attach	= tidss_oldi_bridge_attach,
 	.atomic_pre_enable = tidss_oldi_atomic_pre_enable,
@@ -317,6 +340,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.atomic_check = tidss_oldi_bridge_atomic_check,
 };
 
 static int get_oldi_mode(struct device_node *oldi_tx, int *companion_instance)
-- 
2.34.1

Re: [PATCH v3 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Devarsh Thakkar]

On 01/07/25 15:25, Jayesh Choudhary wrote:
> Since OLDI consumes DSS VP clock directly as serial clock, certain
> checks cannot be performed in tidss driver which should be checked
> in oldi driver. Add check for mode clock and set the curr_max_pclk
> field for tidss in case the VP is OLDI.
> 
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
>   drivers/gpu/drm/tidss/tidss_oldi.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
> index 63e07c8edeaa..a1f5fb39b32c 100644
> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> @@ -309,6 +309,29 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>   	return input_fmts;
>   }
>   
> +static int tidss_oldi_bridge_atomic_check(struct drm_bridge *bridge,
> +					  struct drm_bridge_state *bridge_state,
> +					  struct drm_crtc_state *crtc_state,
> +					  struct drm_connector_state *conn_state)
> +{
> +	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
> +	struct drm_display_mode *adjusted_mode;
> +	unsigned long round_clock;
> +
> +	adjusted_mode = &crtc_state->adjusted_mode;
> +
> +	if (adjusted_mode->clock > oldi->tidss->curr_max_pclk[oldi->parent_vp]) {
> +		round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
> +
> +		if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
> +			return -EINVAL;
> +
> +		oldi->tidss->curr_max_pclk[oldi->parent_vp] = round_clock;
> +	}
> +
> +	return 0;
> +}
> +
>   static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
>   	.attach	= tidss_oldi_bridge_attach,
>   	.atomic_pre_enable = tidss_oldi_atomic_pre_enable,
> @@ -317,6 +340,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
>   	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>   	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
>   	.atomic_reset = drm_atomic_helper_bridge_reset,
> +	.atomic_check = tidss_oldi_bridge_atomic_check,


Nitpick: looks like some mismatch in naming convention.
We don't use bridge for other atomic calls for e.g. 
tidss_oldi_atomic_pre_enable, tidss_oldi_atomic_post_disable so maybe 
change those too ?

With suggested change,

Reviewed-by: Devarsh Thakkar <devarsht@ti.com>

Regards
Devarsh

>   };
>   
>   static int get_oldi_mode(struct device_node *oldi_tx, int *companion_instance)

Re: [PATCH v3 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Jayesh Choudhary]

Hello Devarsh,

On 01/07/25 19:22, Devarsh Thakkar wrote:
> On 01/07/25 15:25, Jayesh Choudhary wrote:
>> Since OLDI consumes DSS VP clock directly as serial clock, certain
>> checks cannot be performed in tidss driver which should be checked
>> in oldi driver. Add check for mode clock and set the curr_max_pclk
>> field for tidss in case the VP is OLDI.
>>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>>   drivers/gpu/drm/tidss/tidss_oldi.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c 
>> b/drivers/gpu/drm/tidss/tidss_oldi.c
>> index 63e07c8edeaa..a1f5fb39b32c 100644
>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
>> @@ -309,6 +309,29 @@ static u32 
>> *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>       return input_fmts;
>>   }
>> +static int tidss_oldi_bridge_atomic_check(struct drm_bridge *bridge,
>> +                      struct drm_bridge_state *bridge_state,
>> +                      struct drm_crtc_state *crtc_state,
>> +                      struct drm_connector_state *conn_state)
>> +{
>> +    struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
>> +    struct drm_display_mode *adjusted_mode;
>> +    unsigned long round_clock;
>> +
>> +    adjusted_mode = &crtc_state->adjusted_mode;
>> +
>> +    if (adjusted_mode->clock > 
>> oldi->tidss->curr_max_pclk[oldi->parent_vp]) {
>> +        round_clock = clk_round_rate(oldi->serial, 
>> adjusted_mode->clock * 7 * 1000);
>> +
>> +        if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, 
>> round_clock) > 5)
>> +            return -EINVAL;
>> +
>> +        oldi->tidss->curr_max_pclk[oldi->parent_vp] = round_clock;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>>   static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
>>       .attach    = tidss_oldi_bridge_attach,
>>       .atomic_pre_enable = tidss_oldi_atomic_pre_enable,
>> @@ -317,6 +340,7 @@ static const struct drm_bridge_funcs 
>> tidss_oldi_bridge_funcs = {
>>       .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>>       .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
>>       .atomic_reset = drm_atomic_helper_bridge_reset,
>> +    .atomic_check = tidss_oldi_bridge_atomic_check,
> 
> 
> Nitpick: looks like some mismatch in naming convention.
> We don't use bridge for other atomic calls for e.g. 
> tidss_oldi_atomic_pre_enable, tidss_oldi_atomic_post_disable so maybe 
> change those too ?

Will change in v4.

Thanks,
Jayesh

> 
> With suggested change,
> 
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> 
> Regards
> Devarsh
> 
>>   };
>>   static int get_oldi_mode(struct device_node *oldi_tx, int 
>> *companion_instance)

Re: [PATCH v3 0/3] Decouple max_pclk check from constant display feats

[Devarsh Thakkar]

On 01/07/25 15:25, Jayesh Choudhary wrote:
> In an effort to make the existing compatibles more usable, we are
> removing the max_pclk_khz form dispc_features structure and doing the
> correspondig checks using "curr_max_pclk[]".
> 
> Changes are fully backwards compatible.
> 
> After integration of OLDI support[0], we need additional patches in
> oldi to identify the VP that has OLDI. We have to do this since
> OLDI driver owns the VP clock (its serial clock) and we cannot perform
> clock operations on those VP clock from tidss driver. This issue was
> also reported upstream when DSI fixes[1] had some clock related calls
> in tidss driver. When "clk_round_rate()" is called, ideally it should
> have gone to "sci_clk_determine_rate()" to query DM but it doesn't since
> clock is owned by OLDI not tidss.
> 

As series is fixing above issue (abnormal behaviour while calling 
clk_round_rate from tidss for VP clock being used by OLDI), can we add 
"Fixes tag" for the patches?

Regards
Devarsh

Re: [PATCH v3 0/3] Decouple max_pclk check from constant display feats

[Jayesh Choudhary]

Hello Devarsh,

On 01/07/25 19:00, Devarsh Thakkar wrote:
> On 01/07/25 15:25, Jayesh Choudhary wrote:
>> In an effort to make the existing compatibles more usable, we are
>> removing the max_pclk_khz form dispc_features structure and doing the
>> correspondig checks using "curr_max_pclk[]".
>>
>> Changes are fully backwards compatible.
>>
>> After integration of OLDI support[0], we need additional patches in
>> oldi to identify the VP that has OLDI. We have to do this since
>> OLDI driver owns the VP clock (its serial clock) and we cannot perform
>> clock operations on those VP clock from tidss driver. This issue was
>> also reported upstream when DSI fixes[1] had some clock related calls
>> in tidss driver. When "clk_round_rate()" is called, ideally it should
>> have gone to "sci_clk_determine_rate()" to query DM but it doesn't since
>> clock is owned by OLDI not tidss.
>>
> 
> As series is fixing above issue (abnormal behaviour while calling 
> clk_round_rate from tidss for VP clock being used by OLDI), can we add 
> "Fixes tag" for the patches?


This seems like a preemptive fix. So I was not sure what to add.

If it should be added then which commit?
7246e0929945 ("drm/tidss: Add OLDI bridge support") ?

Warm Regards,
Jayesh

> 
> Regards
> Devarsh

Re: [PATCH v3 0/3] Decouple max_pclk check from constant display feats

[Devarsh Thakkar]

On 02/07/25 12:31, Jayesh Choudhary wrote:
> Hello Devarsh,
> 
> On 01/07/25 19:00, Devarsh Thakkar wrote:
>> On 01/07/25 15:25, Jayesh Choudhary wrote:
>>> In an effort to make the existing compatibles more usable, we are
>>> removing the max_pclk_khz form dispc_features structure and doing the
>>> correspondig checks using "curr_max_pclk[]".
>>>
>>> Changes are fully backwards compatible.
>>>
>>> After integration of OLDI support[0], we need additional patches in
>>> oldi to identify the VP that has OLDI. We have to do this since
>>> OLDI driver owns the VP clock (its serial clock) and we cannot perform
>>> clock operations on those VP clock from tidss driver. This issue was
>>> also reported upstream when DSI fixes[1] had some clock related calls
>>> in tidss driver. When "clk_round_rate()" is called, ideally it should
>>> have gone to "sci_clk_determine_rate()" to query DM but it doesn't since
>>> clock is owned by OLDI not tidss.
>>>
>>
>> As series is fixing above issue (abnormal behaviour while calling 
>> clk_round_rate from tidss for VP clock being used by OLDI), can we add 
>> "Fixes tag" for the patches?
> 
> 
> This seems like a preemptive fix. So I was not sure what to add.
> 
> If it should be added then which commit?
> 7246e0929945 ("drm/tidss: Add OLDI bridge support") ?
> 

Yes, this looks good. I think good to add it as a bug fix since 
otherwise it causes an abnormal behavior while setting up the VP clock 
from tidss.

Regards
Devarsh


> Warm Regards,
> Jayesh
> 
>>
>> Regards
>> Devarsh