Re: [PATCH v9 10/12] perf/x86: Expose number of Topdown metric events to KVM

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>

On 9/19/2026 3:39 AM, Zide Chen wrote:
> The number of Topdown metric events varies by CPU: ICL/TGL/RKL
> support 4, while SPR/GNR/DMR and some hybrid CPUs support 8.
>
> Add num_topdown_events to struct x86_pmu_capability and populate it
> in perf_get_x86_pmu_capability() so that KVM can determine how many
> PERF_METRICS fields are valid on the host CPU and correctly identify
> the reserved bits in IA32_PERF_METRICS.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> ---
> v9: new patch
> ---
>  arch/x86/events/core.c            | 1 +
>  arch/x86/include/asm/perf_event.h | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index 8b3ea0adb965..01c1c9447f30 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -3164,6 +3164,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
>  	cap->events_mask_len	= x86_pmu.events_mask_len;
>  	cap->pebs_ept		= x86_pmu.pebs_ept;
>  	cap->mediated		= !!(pmu.capabilities & PERF_PMU_CAP_MEDIATED_VPMU);
> +	cap->num_topdown_events	= x86_pmu.num_topdown_events;
>  }
>  EXPORT_SYMBOL_FOR_KVM(perf_get_x86_pmu_capability);
>  
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index ceb6188e5217..3c02389b2ea6 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -306,6 +306,7 @@ struct x86_pmu_capability {
>  	int		bit_width_fixed;
>  	unsigned int	events_mask;
>  	int		events_mask_len;
> +	int		num_topdown_events;
>  	unsigned int	pebs_ept	:1;
>  	unsigned int	mediated	:1;
>  };