* [PATCH 2/4] arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node
2026-03-02 18:17 [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Brandon Brnich
@ 2026-03-02 18:17 ` Brandon Brnich
2026-03-02 18:17 ` [PATCH 3/4] arm64: dts: ti: k3-am62a-main: " Brandon Brnich
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Brandon Brnich @ 2026-03-02 18:17 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: b-brnich
The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.
Signed-off-by: Brandon Brnich <b-brnich@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 7b1ba34ab719..27061918e463 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -717,6 +717,7 @@ vpu: video-codec@4210000 {
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 179 2>;
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ sram = <&main_navss_sram>;
};
main_sdhci0: mmc@4f80000 {
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/4] arm64: dts: ti: k3-am62a-main: Assign SRAM to VPU node
2026-03-02 18:17 [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Brandon Brnich
2026-03-02 18:17 ` [PATCH 2/4] arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node Brandon Brnich
@ 2026-03-02 18:17 ` Brandon Brnich
2026-03-02 18:18 ` [PATCH 4/4] arm64: dts: ti: k3-am62p-j722s-common-main: " Brandon Brnich
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Brandon Brnich @ 2026-03-02 18:17 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: b-brnich
The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.
Signed-off-by: Brandon Brnich <b-brnich@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 9e5b75a4e88e..92dd1b96cef4 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -1149,6 +1149,7 @@ vpu: video-codec@30210000 {
reg = <0x00 0x30210000 0x00 0x10000>;
clocks = <&k3_clks 204 2>;
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+ sram = <&oc_sram>;
};
c7x_0: dsp@7e000000 {
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 4/4] arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node
2026-03-02 18:17 [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Brandon Brnich
2026-03-02 18:17 ` [PATCH 2/4] arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node Brandon Brnich
2026-03-02 18:17 ` [PATCH 3/4] arm64: dts: ti: k3-am62a-main: " Brandon Brnich
@ 2026-03-02 18:18 ` Brandon Brnich
2026-03-03 14:04 ` [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Andrew Davis
2026-03-09 7:27 ` Vignesh Raghavendra
4 siblings, 0 replies; 7+ messages in thread
From: Brandon Brnich @ 2026-03-02 18:18 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: b-brnich
The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.
Signed-off-by: Brandon Brnich <b-brnich@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 0e1af2a69ca2..33deb4a37a65 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1116,6 +1116,7 @@ vpu: video-codec@30210000 {
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 204 2>;
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+ sram = <&oc_sram>;
};
hsm: remoteproc@43c00000 {
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
2026-03-02 18:17 [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Brandon Brnich
` (2 preceding siblings ...)
2026-03-02 18:18 ` [PATCH 4/4] arm64: dts: ti: k3-am62p-j722s-common-main: " Brandon Brnich
@ 2026-03-03 14:04 ` Andrew Davis
2026-03-09 7:27 ` Vignesh Raghavendra
4 siblings, 0 replies; 7+ messages in thread
From: Andrew Davis @ 2026-03-03 14:04 UTC (permalink / raw)
To: Brandon Brnich, nm, vigneshr, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
On 3/2/26 12:17 PM, Brandon Brnich wrote:
> The NavigatorSS (NAVSS) address space contains a 64 KiB on-chip SRAM
> region at its base address. Add an mmio-sram node to expose this region
> to consumers via the generic SRAM allocator API.
>
> Signed-off-by: Brandon Brnich <b-brnich@ti.com>
> ---
Reviewed-by: Andrew Davis <afd@ti.com>
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 80c51b11ac9f..7b1ba34ab719 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -785,6 +785,14 @@ main_navss: bus@30000000 {
> dma-coherent;
> dma-ranges;
>
> + main_navss_sram: navss-sram@30000000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x30000000 0x00 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x00 0x30000000 0x10000>;
> + };
> +
> main_navss_intr: interrupt-controller@310e0000 {
> compatible = "ti,sci-intr";
> reg = <0x00 0x310e0000 0x00 0x4000>;
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
2026-03-02 18:17 [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Brandon Brnich
` (3 preceding siblings ...)
2026-03-03 14:04 ` [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss Andrew Davis
@ 2026-03-09 7:27 ` Vignesh Raghavendra
2026-03-09 15:42 ` Brandon Brnich
4 siblings, 1 reply; 7+ messages in thread
From: Vignesh Raghavendra @ 2026-03-09 7:27 UTC (permalink / raw)
To: Brandon Brnich, nm, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
On 02/03/26 23:47, Brandon Brnich wrote:
> The NavigatorSS (NAVSS) address space contains a 64 KiB on-chip SRAM
> region at its base address. Add an mmio-sram node to expose this region
> to consumers via the generic SRAM allocator API.
>
> Signed-off-by: Brandon Brnich <b-brnich@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 80c51b11ac9f..7b1ba34ab719 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -785,6 +785,14 @@ main_navss: bus@30000000 {
> dma-coherent;
> dma-ranges;
>
> + main_navss_sram: navss-sram@30000000 {
This fails make dtbs_check
> + compatible = "mmio-sram";
> + reg = <0x00 0x30000000 0x00 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x00 0x30000000 0x10000>;
> + };
> +
> main_navss_intr: interrupt-controller@310e0000 {
> compatible = "ti,sci-intr";
> reg = <0x00 0x310e0000 0x00 0x4000>;
--
Regards
Vignesh
https://ti.com/opensource
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
2026-03-09 7:27 ` Vignesh Raghavendra
@ 2026-03-09 15:42 ` Brandon Brnich
0 siblings, 0 replies; 7+ messages in thread
From: Brandon Brnich @ 2026-03-09 15:42 UTC (permalink / raw)
To: Vignesh Raghavendra, nm, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
Hi Vignesh,
On 3/9/26 02:27, Vignesh Raghavendra wrote:
>
>
> On 02/03/26 23:47, Brandon Brnich wrote:
>> The NavigatorSS (NAVSS) address space contains a 64 KiB on-chip SRAM
>> region at its base address. Add an mmio-sram node to expose this region
>> to consumers via the generic SRAM allocator API.
>>
>> Signed-off-by: Brandon Brnich <b-brnich@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 80c51b11ac9f..7b1ba34ab719 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> @@ -785,6 +785,14 @@ main_navss: bus@30000000 {
>> dma-coherent;
>> dma-ranges;
>>
>> + main_navss_sram: navss-sram@30000000 {
>
> This fails make dtbs_check
I ran kpv but must be having configuration issues because all of these
cases passed. I will fixup the node and send a v2 shortly.
Best,
Brandon
>
>> + compatible = "mmio-sram";
>> + reg = <0x00 0x30000000 0x00 0x10000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x00 0x30000000 0x10000>;
>> + };
>> +
>> main_navss_intr: interrupt-controller@310e0000 {
>> compatible = "ti,sci-intr";
>> reg = <0x00 0x310e0000 0x00 0x4000>;
>
^ permalink raw reply [flat|nested] 7+ messages in thread