* [PATCH v1 1/8] x86/sev: Make SVSM calls preemption-safe
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 2/8] x86/sev: Add support for Alternate Injection Melody Wang
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
Two functions in the the SVSM vTPM guest implementation do not disable
preemption when fetching CAA.
The SVSM calling area is a per-CPU structure. When a thread is preempted
and migrated to a different CPU after fetching the per-CPU Calling Area
Address (CAA), the SVSM call will execute on the new CPU with the
original CPU's CAA. Which is wrong.
Move the CAA fetching operation inside svsm_perform_call_protocol()
which disables interrupts around the SVSM call and thus runs
preemption-safe.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/coco/sev/svsm.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/coco/sev/svsm.c b/arch/x86/coco/sev/svsm.c
index 916d62cd17dc..92ea93f506c0 100644
--- a/arch/x86/coco/sev/svsm.c
+++ b/arch/x86/coco/sev/svsm.c
@@ -74,6 +74,15 @@ int svsm_perform_call_protocol(struct svsm_call *call)
flags = native_local_irq_save();
+ /*
+ * 'caa' is a per-CPU variable. To avoid using a stale or incorrect
+ * 'caa' if the task is preempted or migrates to another CPU after it
+ * is fetched, always fetch 'caa' and then issue the SVSM call with
+ * interrupts disabled. This ensures the correct 'caa' is used even
+ * under preemption or CPU migration.
+ */
+ call->caa = svsm_get_caa();
+
ghcb = __sev_get_ghcb(&state);
do {
@@ -321,7 +330,6 @@ int snp_svsm_vtpm_send_command(u8 *buffer)
{
struct svsm_call call = {};
- call.caa = svsm_get_caa();
call.rax = SVSM_VTPM_CALL(SVSM_VTPM_CMD);
call.rcx = __pa(buffer);
@@ -345,7 +353,6 @@ bool snp_svsm_vtpm_probe(void)
if (!snp_vmpl)
return false;
- call.caa = svsm_get_caa();
call.rax = SVSM_VTPM_CALL(SVSM_VTPM_QUERY);
if (svsm_perform_call_protocol(&call))
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 2/8] x86/sev: Add support for Alternate Injection
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
2026-08-29 3:39 ` [PATCH v1 1/8] x86/sev: Make SVSM calls preemption-safe Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 3/8] x86/apic: Add an SVSM APIC driver Melody Wang
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
The Alternate Injection feature is a method to protect an AMD
confidential computing guest from malicious injection attacks. It allows
the guest to control the interrupt injection.
When this feature is enabled, interrupts are injected with the help of
an agent called a Secure VM Service Module (SVSM) which executes in the
security realm of the guest and uses Restricted Injection as the sole
method to receive interrupts from the hypervisor.
Add support for Alternate Injection enablement.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/Kconfig | 14 ++++++++++++++
arch/x86/boot/compressed/sev.c | 2 +-
arch/x86/coco/core.c | 3 +++
arch/x86/coco/sev/core.c | 2 +-
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/msr-index.h | 4 ++--
include/linux/cc_platform.h | 8 ++++++++
7 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 15fd9ec5ecac..6709589aaa46 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -497,6 +497,20 @@ config AMD_SECURE_AVIC
If you don't know what to do here, say N.
+config AMD_ALTERNATE_INJ
+ bool "Support Alternate Injection"
+ depends on X86_X2APIC && AMD_MEM_ENCRYPT
+ help
+ Enable AMD Alternate Injection support for SNP guests.
+
+ The Alternate Injection feature of SEV-SNP enhances the security of
+ a confidential VM by preventing the untrusted host from presenting
+ unexpected interrupts or exceptions, while still preserving the
+ standard interrupt dispatch semantics inherent to the x86
+ architecture.
+
+ If you don't know what to do here, say N.
+
config X86_POSTED_MSI
bool "Enable MSI and MSI-x delivery by posted interrupts"
depends on X86_64 && IRQ_REMAP
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index c6512f2ea31e..fc2029746c50 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -179,7 +179,7 @@ bool sev_es_check_ghcb_fault(unsigned long address)
#define SNP_FEATURES_IMPL_REQ (MSR_AMD64_SNP_VTOM | \
MSR_AMD64_SNP_REFLECT_VC | \
MSR_AMD64_SNP_RESTRICTED_INJ | \
- MSR_AMD64_SNP_ALT_INJ | \
+ MSR_AMD64_SNP_ALTERNATE_INJ | \
MSR_AMD64_SNP_DEBUG_SWAP | \
MSR_AMD64_SNP_VMPL_SSS | \
MSR_AMD64_SNP_SECURE_TSC | \
diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
index 989ca9f72ba3..aabda3ddc0e2 100644
--- a/arch/x86/coco/core.c
+++ b/arch/x86/coco/core.c
@@ -107,6 +107,9 @@ static bool noinstr amd_cc_platform_has(enum cc_attr attr)
case CC_ATTR_SNP_SECURE_AVIC:
return sev_status & MSR_AMD64_SNP_SECURE_AVIC;
+ case CC_ATTR_SNP_ALTERNATE_INJECTION:
+ return sev_status & MSR_AMD64_SNP_ALTERNATE_INJ;
+
default:
return false;
}
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index cc292d7c6fd1..c54269366278 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -78,7 +78,7 @@ static const char * const sev_status_feat_names[] = {
[MSR_AMD64_SNP_VTOM_BIT] = "vTom",
[MSR_AMD64_SNP_REFLECT_VC_BIT] = "ReflectVC",
[MSR_AMD64_SNP_RESTRICTED_INJ_BIT] = "RI",
- [MSR_AMD64_SNP_ALT_INJ_BIT] = "AI",
+ [MSR_AMD64_SNP_ALTERNATE_INJ_BIT] = "AI",
[MSR_AMD64_SNP_DEBUG_SWAP_BIT] = "DebugSwap",
[MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT] = "NoHostIBS",
[MSR_AMD64_SNP_BTB_ISOLATION_BIT] = "BTBIsol",
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f70ee74b5f92..a53e40a3982c 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -466,6 +466,7 @@
#define X86_FEATURE_SNP_SECURE_TSC (19*32+ 8) /* SEV-SNP Secure TSC */
#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */
#define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
+#define X86_FEATURE_ALTERNATE_INJECTION (19*32+13) /* SEV Alternate Injection */
#define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
#define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */
#define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3a8e51a0c9e8..473a3ba86a2d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -721,8 +721,8 @@
#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
#define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5
#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
-#define MSR_AMD64_SNP_ALT_INJ_BIT 6
-#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
+#define MSR_AMD64_SNP_ALTERNATE_INJ_BIT 6
+#define MSR_AMD64_SNP_ALTERNATE_INJ BIT_ULL(MSR_AMD64_SNP_ALTERNATE_INJ_BIT)
#define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7
#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
#define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8
diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h
index 559353ad64ac..90ef67e85cd3 100644
--- a/include/linux/cc_platform.h
+++ b/include/linux/cc_platform.h
@@ -104,6 +104,14 @@ enum cc_attr {
* to run SEV-SNP guests with full Secure AVIC capabilities.
*/
CC_ATTR_SNP_SECURE_AVIC,
+
+ /**
+ * @CC_ATTR_SNP_ALTERNATE_INJECTION: AMD Alternate Injection enabled on the host.
+ *
+ * The host kernel is running with the necessary features
+ * needed to run Alternate Injection enabled guests.
+ */
+ CC_ATTR_SNP_ALTERNATE_INJECTION,
};
#ifdef CONFIG_ARCH_HAS_CC_PLATFORM
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 3/8] x86/apic: Add an SVSM APIC driver
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
2026-08-29 3:39 ` [PATCH v1 1/8] x86/sev: Make SVSM calls preemption-safe Melody Wang
2026-08-29 3:39 ` [PATCH v1 2/8] x86/sev: Add support for Alternate Injection Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 4/8] x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation Melody Wang
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
Alternate Injection replaces hypervisor-based interrupt queuing and
event injection, requiring guest-controlled queuing and injection. In
order to perform this guest-controlled queuing and injectiion, an SVSM
is used to update the guest VMSA to perform the required actions.
The guest uses the SVSM APIC protocol to communicate with the SVSM to
perform selected APIC related operations instead of using standard APIC
MSR access.
Add such a SVSM APIC driver (which implements a subset of an X2APIC),
for the APIC emulation supported by the SVSM.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/include/asm/sev-common.h | 1 +
arch/x86/include/asm/sev.h | 9 ++
arch/x86/kernel/apic/Makefile | 1 +
arch/x86/kernel/apic/x2apic_svsm.c | 233 +++++++++++++++++++++++++++++
4 files changed, 244 insertions(+)
create mode 100644 arch/x86/kernel/apic/x2apic_svsm.c
diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
index 01a6e4dbe423..095fbafe8a2c 100644
--- a/arch/x86/include/asm/sev-common.h
+++ b/arch/x86/include/asm/sev-common.h
@@ -209,6 +209,7 @@ struct snp_psc_desc {
#define GHCB_TERM_SECURE_TSC 10 /* Secure TSC initialization failed */
#define GHCB_TERM_SVSM_CA_REMAP_FAIL 11 /* SVSM is present but CA could not be remapped */
#define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */
+#define GHCB_TERM_ALT_INJ_FAIL 13 /* Alternate Injection-specific failure */
#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index 9e7a077c445d..557c4d1ef4be 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -435,6 +435,13 @@ struct svsm_call {
#define SVSM_VTPM_QUERY 0
#define SVSM_VTPM_CMD 1
+#define SVSM_APIC_CALL(x) ((3ULL << 32) | (x))
+#define SVSM_APIC_QUERY_FEATURES 0
+#define SVSM_APIC_CONFIG_EMULATION 1
+#define SVSM_APIC_READ_REGISTER 2
+#define SVSM_APIC_WRITE_REGISTER 3
+#define SVSM_APIC_CONFIG_VECTOR 4
+
#ifdef CONFIG_AMD_MEM_ENCRYPT
extern u8 snp_vmpl;
@@ -528,6 +535,7 @@ void snp_msg_free(struct snp_msg_desc *mdesc);
int snp_send_guest_request(struct snp_msg_desc *mdesc, struct snp_guest_req *req);
int snp_svsm_vtpm_send_command(u8 *buffer);
+int svsm_perform_call_protocol(struct svsm_call *call);
void __init snp_secure_tsc_prepare(void);
void __init snp_secure_tsc_init(void);
@@ -636,6 +644,7 @@ static inline void snp_msg_free(struct snp_msg_desc *mdesc) { }
static inline int snp_send_guest_request(struct snp_msg_desc *mdesc,
struct snp_guest_req *req) { return -ENODEV; }
static inline int snp_svsm_vtpm_send_command(u8 *buffer) { return -ENODEV; }
+static inline int svsm_perform_call_protocol(struct svsm_call *call) { return -ENODEV; }
static inline void __init snp_secure_tsc_prepare(void) { }
static inline void __init snp_secure_tsc_init(void) { }
static inline void sev_evict_cache(void *va, int npages) {}
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 581db89477f9..23d83f1293e3 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_SMP) += ipi.o
ifeq ($(CONFIG_X86_64),y)
# APIC probe will depend on the listing order here
obj-$(CONFIG_X86_NUMACHIP) += apic_numachip.o
+obj-$(CONFIG_AMD_ALTERNATE_INJ) += x2apic_svsm.o
obj-$(CONFIG_X86_UV) += x2apic_uv_x.o
obj-$(CONFIG_AMD_SECURE_AVIC) += x2apic_savic.o
obj-$(CONFIG_X86_X2APIC) += x2apic_phys.o
diff --git a/arch/x86/kernel/apic/x2apic_svsm.c b/arch/x86/kernel/apic/x2apic_svsm.c
new file mode 100644
index 000000000000..b553bfde4b85
--- /dev/null
+++ b/arch/x86/kernel/apic/x2apic_svsm.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * AMD Alternate Injection Support (SEV-SNP Guests)
+ *
+ * Copyright (C) 2026 Advanced Micro Devices, Inc.
+ *
+ * Author: Melody Wang <huibo.wang@amd.com>
+ */
+
+#include <linux/cpumask.h>
+#include <linux/cc_platform.h>
+
+#include <asm/apic.h>
+#include <asm/sev.h>
+
+#include "local.h"
+
+static int svsm_apic_probe(void)
+{
+ if (cc_platform_has(CC_ATTR_SNP_ALTERNATE_INJECTION) && !snp_vmpl) {
+ pr_err("Alternate Injection in VMPL0 impossible. Terminating.\n");
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+
+ if (!cc_platform_has(CC_ATTR_SNP_ALTERNATE_INJECTION))
+ return 0;
+
+ if (!x2apic_mode) {
+ pr_err("Alternate Injection in non x2APIC mode impossible. Terminating.\n");
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+
+ pr_info("Alternate Injection SVSM APIC enabled\n");
+
+ return 1;
+}
+
+static int svsm_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+ return x2apic_enabled() && cc_platform_has(CC_ATTR_SNP_ALTERNATE_INJECTION) && snp_vmpl;
+}
+
+static u32 __svsm_apic_msr_rw(u32 reg, u32 v, bool write)
+{
+ u32 msr = APIC_BASE_MSR + (reg >> 4);
+ struct svsm_call call = {};
+ const char *call_reg_str;
+ unsigned int call_reg;
+ int ret;
+
+ call_reg = write ? SVSM_APIC_WRITE_REGISTER
+ : SVSM_APIC_READ_REGISTER;
+
+ call_reg_str = write ? "SVSM_APIC_WRITE_REGISTER"
+ : "SVSM_APIC_READ_REGISTER";
+
+ switch (reg) {
+ case APIC_ID:
+ case APIC_TASKPRI:
+ case APIC_PROCPRI:
+ case APIC_EOI:
+ case APIC_ISR ... APIC_ISR + 0x70:
+ case APIC_TMR ... APIC_TMR + 0x70:
+ case APIC_IRR ... APIC_IRR + 0x70:
+ case APIC_ICR:
+ case APIC_SELF_IPI:
+ call.rax = SVSM_APIC_CALL(call_reg);
+ call.rcx = msr;
+ call.rdx = v;
+
+ ret = svsm_perform_call_protocol(&call);
+ if (ret) {
+ pr_err("%s: 0x%x, error: %d\n", call_reg_str, reg, ret);
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+ break;
+ default:
+ pr_err("%s 0x%x not supported\n", call_reg_str, reg);
+ return 0;
+ }
+
+ return call.rdx_out;
+}
+
+static void svsm_apic_msr_write(u32 reg, u32 v)
+{
+ __svsm_apic_msr_rw(reg, v, true);
+}
+
+
+static u32 svsm_apic_msr_read(u32 reg)
+{
+ return __svsm_apic_msr_rw(reg, 0, false);
+}
+
+static inline void svsm_apic_msr_eoi(void)
+{
+ svsm_apic_msr_write(APIC_EOI, APIC_EOI_ACK);
+}
+
+static inline u64 svsm_apic_icr_read(void)
+{
+ struct svsm_call call = {};
+ u32 reg;
+ int ret;
+
+ reg = APIC_ICR;
+
+ call.rax = SVSM_APIC_CALL(SVSM_APIC_READ_REGISTER);
+ call.rcx = APIC_BASE_MSR + (reg >> 4);
+
+ ret = svsm_perform_call_protocol(&call);
+ if (ret) {
+ pr_err("svsm_apic_icr_read error: %d\n", ret);
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+
+ return call.rdx_out;
+}
+
+static void svsm_apic_icr_write(u32 low, u32 id)
+{
+ struct svsm_call call = {};
+ u64 icr_data;
+ u32 reg;
+ int ret;
+
+ reg = APIC_ICR;
+ icr_data = ((u64)id) << 32 | low;
+
+ call.rax = SVSM_APIC_CALL(SVSM_APIC_WRITE_REGISTER);
+ call.rcx = APIC_BASE_MSR + (reg >> 4);
+ call.rdx = icr_data;
+
+ ret = svsm_perform_call_protocol(&call);
+ if (ret) {
+ pr_err("svsm_apic_icr_write error: %d\n", ret);
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+}
+
+static void svsm_apic_send_IPI(int cpu, int vector)
+{
+ u32 dest = per_cpu(x86_cpu_to_apicid, cpu);
+
+ svsm_apic_icr_write(__prepare_ICR(0, vector, APIC_DEST_PHYSICAL), dest);
+}
+
+static void __svsm_apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
+{
+ unsigned long query_cpu;
+ unsigned long this_cpu;
+
+ guard(irqsave)();
+
+ this_cpu = smp_processor_id();
+ for_each_cpu(query_cpu, mask) {
+ if (apic_dest == APIC_DEST_ALLBUT && this_cpu == query_cpu)
+ continue;
+
+ svsm_apic_send_IPI(query_cpu, vector);
+ }
+}
+
+static void svsm_apic_send_IPI_mask(const struct cpumask *mask, int vector)
+{
+ __svsm_apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
+}
+
+static void svsm_apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
+{
+ __svsm_apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
+}
+
+static void __svsm_apic_send_IPI_shorthand(int vector, u32 which)
+{
+ svsm_apic_icr_write(__prepare_ICR(which, vector, 0), 0);
+}
+
+static void svsm_apic_send_IPI_allbutself(int vector)
+{
+ __svsm_apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT);
+}
+
+static void svsm_apic_send_IPI_all(int vector)
+{
+ __svsm_apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC);
+}
+
+static void svsm_apic_send_IPI_self(int vector)
+{
+ __svsm_apic_send_IPI_shorthand(vector, APIC_DEST_SELF);
+}
+
+static u32 svsm_apic_get_apic_id(u32 id)
+{
+ return id;
+}
+
+static struct apic svsm_apic __ro_after_init = {
+
+ .name = "svsm apic",
+ .probe = svsm_apic_probe,
+ .acpi_madt_oem_check = svsm_acpi_madt_oem_check,
+
+ .dest_mode_logical = false,
+
+ .disable_esr = 0,
+
+ .cpu_present_to_apicid = default_cpu_present_to_apicid,
+
+ .max_apic_id = UINT_MAX,
+ .x2apic_set_max_apicid = true,
+ .get_apic_id = svsm_apic_get_apic_id,
+
+ .calc_dest_apicid = apic_default_calc_apicid,
+
+ .send_IPI = svsm_apic_send_IPI,
+ .send_IPI_mask = svsm_apic_send_IPI_mask,
+ .send_IPI_mask_allbutself = svsm_apic_send_IPI_mask_allbutself,
+ .send_IPI_allbutself = svsm_apic_send_IPI_allbutself,
+ .send_IPI_all = svsm_apic_send_IPI_all,
+ .send_IPI_self = svsm_apic_send_IPI_self,
+ .nmi_to_offline_cpu = true,
+
+ .read = svsm_apic_msr_read,
+ .write = svsm_apic_msr_write,
+ .eoi = svsm_apic_msr_eoi,
+ .icr_read = svsm_apic_icr_read,
+ .icr_write = svsm_apic_icr_write,
+
+};
+apic_driver(svsm_apic);
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 4/8] x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
` (2 preceding siblings ...)
2026-08-29 3:39 ` [PATCH v1 3/8] x86/apic: Add an SVSM APIC driver Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 5/8] x86/sev: Add a function to contain all SEV-specific setup operations Melody Wang
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
The SVSM APIC emulation supports only a subset of the X2APIC MSRs.
Right now only basic APIC functionality related to interrupt delivery is
supported. Therefore, route the unsupported ones to the hypervisor's
X2APIC emulation.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/coco/sev/core.c | 12 ++++++------
arch/x86/include/asm/sev-common.h | 1 +
arch/x86/include/asm/sev.h | 8 ++++----
arch/x86/kernel/apic/x2apic_savic.c | 8 ++++----
arch/x86/kernel/apic/x2apic_svsm.c | 9 ++++++---
5 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index c54269366278..ec8fc02bd636 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -972,7 +972,7 @@ int __init sev_es_efi_map_ghcbs_cas(pgd_t *pgd)
return 0;
}
-u64 savic_ghcb_msr_read(u32 reg)
+u64 sev_apic_ghcb_msr_read(u32 reg)
{
u64 msr = APIC_BASE_MSR + (reg >> 4);
struct pt_regs regs = { .cx = msr };
@@ -988,9 +988,9 @@ u64 savic_ghcb_msr_read(u32 reg)
res = __vc_handle_msr(ghcb, &ctxt, false);
if (res != ES_OK) {
- pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res);
+ pr_err("APIC MSR via GHCB (0x%llx) read returned error (%d)\n", msr, res);
/* MSR read failures are treated as fatal errors */
- sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL);
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL);
}
__sev_put_ghcb(&state);
@@ -998,7 +998,7 @@ u64 savic_ghcb_msr_read(u32 reg)
return regs.ax | regs.dx << 32;
}
-void savic_ghcb_msr_write(u32 reg, u64 value)
+void sev_apic_ghcb_msr_write(u32 reg, u64 value)
{
u64 msr = APIC_BASE_MSR + (reg >> 4);
struct pt_regs regs = {
@@ -1018,9 +1018,9 @@ void savic_ghcb_msr_write(u32 reg, u64 value)
res = __vc_handle_msr(ghcb, &ctxt, true);
if (res != ES_OK) {
- pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res);
+ pr_err("APIC MSR via GHCB (0x%llx) write returned error (%d)\n", msr, res);
/* MSR writes should never fail. Any failure is fatal error for SNP guest */
- sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL);
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL);
}
__sev_put_ghcb(&state);
diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h
index 095fbafe8a2c..585ddc44b6b4 100644
--- a/arch/x86/include/asm/sev-common.h
+++ b/arch/x86/include/asm/sev-common.h
@@ -210,6 +210,7 @@ struct snp_psc_desc {
#define GHCB_TERM_SVSM_CA_REMAP_FAIL 11 /* SVSM is present but CA could not be remapped */
#define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */
#define GHCB_TERM_ALT_INJ_FAIL 13 /* Alternate Injection-specific failure */
+#define GHCB_TERM_APIC_MSR_FAIL 14 /* APIC MSR failure */
#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index 557c4d1ef4be..3cb6c5d6a6e0 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -541,8 +541,8 @@ void __init snp_secure_tsc_prepare(void);
void __init snp_secure_tsc_init(void);
enum es_result savic_register_gpa(u64 gpa);
enum es_result savic_unregister_gpa(u64 *gpa);
-u64 savic_ghcb_msr_read(u32 reg);
-void savic_ghcb_msr_write(u32 reg, u64 value);
+u64 sev_apic_ghcb_msr_read(u32 reg);
+void sev_apic_ghcb_msr_write(u32 reg, u64 value);
static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb)
{
@@ -650,8 +650,8 @@ static inline void __init snp_secure_tsc_init(void) { }
static inline void sev_evict_cache(void *va, int npages) {}
static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; }
static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; }
-static inline void savic_ghcb_msr_write(u32 reg, u64 value) { }
-static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; }
+static inline void sev_apic_ghcb_msr_write(u32 reg, u64 value) { }
+static inline u64 sev_apic_ghcb_msr_read(u32 reg) { return 0; }
#endif /* CONFIG_AMD_MEM_ENCRYPT */
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index 4bc6d7e018a5..990e4a379e07 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -72,7 +72,7 @@ static u32 savic_read(u32 reg)
case APIC_LVT0:
case APIC_LVT1:
case APIC_LVTERR:
- return savic_ghcb_msr_read(reg);
+ return sev_apic_ghcb_msr_read(reg);
case APIC_ID:
case APIC_LVR:
case APIC_TASKPRI:
@@ -193,7 +193,7 @@ static void savic_icr_write(u32 icr_low, u32 icr_high)
icr_data = ((u64)icr_high) << 32 | icr_low;
if (dsh != APIC_DEST_SELF)
- savic_ghcb_msr_write(APIC_ICR, icr_data);
+ sev_apic_ghcb_msr_write(APIC_ICR, icr_data);
apic_set_reg64(this_cpu_ptr(savic_page), APIC_ICR, icr_data);
}
@@ -210,7 +210,7 @@ static void savic_write(u32 reg, u32 data)
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_LVTERR:
- savic_ghcb_msr_write(reg, data);
+ sev_apic_ghcb_msr_write(reg, data);
break;
case APIC_TASKPRI:
case APIC_EOI:
@@ -316,7 +316,7 @@ static void savic_eoi(void)
* interrupts. Return to the guest from GHCB protocol event takes
* care of re-evaluating interrupt state.
*/
- savic_ghcb_msr_write(APIC_EOI, 0);
+ sev_apic_ghcb_msr_write(APIC_EOI, 0);
} else {
/*
* Hardware clears APIC_ISR and re-evaluates the interrupt state
diff --git a/arch/x86/kernel/apic/x2apic_svsm.c b/arch/x86/kernel/apic/x2apic_svsm.c
index b553bfde4b85..1a1aefc26726 100644
--- a/arch/x86/kernel/apic/x2apic_svsm.c
+++ b/arch/x86/kernel/apic/x2apic_svsm.c
@@ -69,14 +69,17 @@ static u32 __svsm_apic_msr_rw(u32 reg, u32 v, bool write)
call.rdx = v;
ret = svsm_perform_call_protocol(&call);
- if (ret) {
+ if (ret) {
pr_err("%s: 0x%x, error: %d\n", call_reg_str, reg, ret);
sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
}
break;
default:
- pr_err("%s 0x%x not supported\n", call_reg_str, reg);
- return 0;
+ if (write) {
+ sev_apic_ghcb_msr_write(reg, v);
+ } else {
+ return sev_apic_ghcb_msr_read(reg);
+ }
}
return call.rdx_out;
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 5/8] x86/sev: Add a function to contain all SEV-specific setup operations
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
` (3 preceding siblings ...)
2026-08-29 3:39 ` [PATCH v1 4/8] x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 6/8] x86/sev: Register the guest with the SVSM APIC protocol Melody Wang
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
To make the code clean in the boot phase, add a sev_prepare() wrapper
which contains early SEV-specific checks in order to have all that code
in a single place.
No functional changes.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/boot/compressed/sev.c | 11 +++++++++++
arch/x86/include/asm/sev.h | 3 +++
drivers/firmware/efi/libstub/x86-stub.c | 17 +++--------------
3 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index fc2029746c50..c935a97f72e9 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -511,3 +511,14 @@ bool early_is_sevsnp_guest(void)
}
return true;
}
+
+bool sev_prepare(void)
+{
+ u64 unsupported = snp_get_unsupported_features(sev_get_status());
+ if (unsupported) {
+ error("Unsupported SEV-SNP features detected\n");
+ return true;
+ }
+
+ return false;
+}
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index 3cb6c5d6a6e0..95f9a5084c45 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -605,6 +605,8 @@ static inline void sev_evict_cache(void *va, int npages)
}
}
+bool sev_prepare(void);
+
#else /* !CONFIG_AMD_MEM_ENCRYPT */
#define snp_vmpl 0
@@ -652,6 +654,7 @@ static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED
static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; }
static inline void sev_apic_ghcb_msr_write(u32 reg, u64 value) { }
static inline u64 sev_apic_ghcb_msr_read(u32 reg) { return 0; }
+static inline bool sev_prepare(void) { return false; }
#endif /* CONFIG_AMD_MEM_ENCRYPT */
diff --git a/drivers/firmware/efi/libstub/x86-stub.c b/drivers/firmware/efi/libstub/x86-stub.c
index cef32e2c82d8..fae3a7dfb8b3 100644
--- a/drivers/firmware/efi/libstub/x86-stub.c
+++ b/drivers/firmware/efi/libstub/x86-stub.c
@@ -783,19 +783,6 @@ static efi_status_t exit_boot(struct boot_params *boot_params, void *handle)
return EFI_SUCCESS;
}
-static bool have_unsupported_snp_features(void)
-{
- u64 unsupported;
-
- unsupported = snp_get_unsupported_features(sev_get_status());
- if (unsupported) {
- efi_err("Unsupported SEV-SNP features detected: 0x%llx\n",
- unsupported);
- return true;
- }
- return false;
-}
-
static void efi_get_seed(void *seed, int size)
{
efi_get_random_bytes(size, seed);
@@ -919,6 +906,7 @@ void __noreturn efi_stub_entry(efi_handle_t handle,
unsigned long kernel_entry;
struct setup_header *hdr;
efi_status_t status;
+ bool err;
efi_system_table = sys_table_arg;
/* Check if we were booted by the EFI firmware */
@@ -933,7 +921,8 @@ void __noreturn efi_stub_entry(efi_handle_t handle,
hdr = &boot_params->hdr;
- if (have_unsupported_snp_features())
+ err = sev_prepare();
+ if (err)
efi_exit(handle, EFI_UNSUPPORTED);
if (IS_ENABLED(CONFIG_EFI_DXE_MEM_ATTRIBUTES)) {
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 6/8] x86/sev: Register the guest with the SVSM APIC protocol
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
` (4 preceding siblings ...)
2026-08-29 3:39 ` [PATCH v1 5/8] x86/sev: Add a function to contain all SEV-specific setup operations Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 7/8] x86/sev: Allow the guest to configure interrupt vectors for the hypervisor Melody Wang
2026-08-29 3:39 ` [PATCH v1 8/8] x86/sev: Indicate that Alternate Injection is supported in the guest Melody Wang
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
The SVSM APIC protocol supports 5 calls. SVSM_APIC_CONFIGURE_EMULATION
(shortened to SVSM_APIC_CONFIG_EMULATION for brevity), call 1, provides
the controls whether the guest can make use of the SVSM APIC protocol.
Implement this call, and register Alternate Injection for the guest
by default.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/boot/compressed/sev.c | 17 +++++++++++++++++
arch/x86/boot/compressed/sev.h | 6 ++++++
2 files changed, 23 insertions(+)
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index c935a97f72e9..a8a175c90fa8 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -520,5 +520,22 @@ bool sev_prepare(void)
return true;
}
+ /* Register Alternate Injection */
+ if (early_is_sevsnp_guest() && snp_vmpl) {
+ struct svsm_call call = {};
+ int ret;
+
+ if (!(sev_get_status() & MSR_AMD64_SNP_ALTERNATE_INJ))
+ return 0;
+
+ call.caa = (struct svsm_ca *)boot_svsm_caa_pa;
+ call.rax = SVSM_APIC_CALL(SVSM_APIC_CONFIG_EMULATION);
+ call.rcx = SVSM_AI_REGISTER;
+
+ ret = svsm_call_msr_protocol(&call);
+ if (ret)
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+ }
+
return false;
}
diff --git a/arch/x86/boot/compressed/sev.h b/arch/x86/boot/compressed/sev.h
index 22637b416b46..dd058af2e7aa 100644
--- a/arch/x86/boot/compressed/sev.h
+++ b/arch/x86/boot/compressed/sev.h
@@ -12,6 +12,12 @@
#include <asm/shared/msr.h>
+enum svsm_ai_ctrl {
+ SVSM_AI_DISABLE,
+ SVSM_AI_DEREGISTER,
+ SVSM_AI_REGISTER,
+};
+
void snp_accept_memory(phys_addr_t start, phys_addr_t end);
u64 sev_get_status(void);
bool early_is_sevsnp_guest(void);
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 7/8] x86/sev: Allow the guest to configure interrupt vectors for the hypervisor
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
` (5 preceding siblings ...)
2026-08-29 3:39 ` [PATCH v1 6/8] x86/sev: Register the guest with the SVSM APIC protocol Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
2026-08-29 3:39 ` [PATCH v1 8/8] x86/sev: Indicate that Alternate Injection is supported in the guest Melody Wang
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
The SVSM APIC protocol supports 5 API calls. SVSM_APIC_CONFIGURE_VECTOR
(shortened to SVSM_APIC_CONFIG_VECTOR for brevity), call 4, provides for
the guest to configure an interrupt vector which the guest allows and
the hypervisor can use to signal interrupts for it.
Implement this call, and make the default interrupt setting permissive
to allow all interrupts when detecting an SVSM and Alternate Injection
is enabled.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/boot/compressed/sev.c | 12 +++++++++++-
arch/x86/boot/compressed/sev.h | 7 +++++++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index a8a175c90fa8..479b74c75b4b 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -520,7 +520,10 @@ bool sev_prepare(void)
return true;
}
- /* Register Alternate Injection */
+ /* When the guest is running at VMPL2 with Alternate Injection enabled,
+ * register Alternate Injection, and configure all of interrupts as
+ * permissive by default.
+ */
if (early_is_sevsnp_guest() && snp_vmpl) {
struct svsm_call call = {};
int ret;
@@ -535,6 +538,13 @@ bool sev_prepare(void)
ret = svsm_call_msr_protocol(&call);
if (ret)
sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
+
+ call.rax = SVSM_APIC_CALL(SVSM_APIC_CONFIG_VECTOR);
+ call.rcx = SVSM_IRQ_ENABLE_ALL;
+
+ ret = svsm_call_msr_protocol(&call);
+ if (svsm_call_msr_protocol(&call))
+ sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL);
}
return false;
diff --git a/arch/x86/boot/compressed/sev.h b/arch/x86/boot/compressed/sev.h
index dd058af2e7aa..035a7b46085b 100644
--- a/arch/x86/boot/compressed/sev.h
+++ b/arch/x86/boot/compressed/sev.h
@@ -18,6 +18,13 @@ enum svsm_ai_ctrl {
SVSM_AI_REGISTER,
};
+enum svsm_vec_enable {
+ SVSM_IRQ_DISABLE_SINGLE = (0u << 8),
+ SVSM_IRQ_ENABLE_SINGLE = (1u << 8),
+ SVSM_IRQ_DISABLE_ALL = (2u << 8),
+ SVSM_IRQ_ENABLE_ALL = (3u << 8),
+};
+
void snp_accept_memory(phys_addr_t start, phys_addr_t end);
u64 sev_get_status(void);
bool early_is_sevsnp_guest(void);
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 8/8] x86/sev: Indicate that Alternate Injection is supported in the guest
2026-08-29 3:39 [PATCH v1 0/8] Alternate Injection: Secure Interrupt Delivery for SEV-SNP Guests - Guest Support Melody Wang
` (6 preceding siblings ...)
2026-08-29 3:39 ` [PATCH v1 7/8] x86/sev: Allow the guest to configure interrupt vectors for the hypervisor Melody Wang
@ 2026-08-29 3:39 ` Melody Wang
7 siblings, 0 replies; 9+ messages in thread
From: Melody Wang @ 2026-08-29 3:39 UTC (permalink / raw)
To: x86; +Cc: LKML, Tom Lendacky, Melody Wang
Now the Alternate Injection support is complete, add it to the present
SNP features.
Signed-off-by: Melody Wang <huibo.wang@amd.com>
---
arch/x86/boot/compressed/sev.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index 479b74c75b4b..cec1ef473691 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -197,6 +197,12 @@ bool sev_es_check_ghcb_fault(unsigned long address)
#define SNP_FEATURE_SECURE_AVIC 0
#endif
+#ifdef CONFIG_AMD_ALTERNATE_INJ
+#define SNP_FEATURE_ALTERNATE_INJ MSR_AMD64_SNP_ALTERNATE_INJ
+#else
+#define SNP_FEATURE_ALTERNATE_INJ 0
+#endif
+
/*
* SNP_FEATURES_IMPL is the mask of SNP features that are implemented
* by the guest kernel. As and when a new feature is implemented in the
@@ -204,7 +210,8 @@ bool sev_es_check_ghcb_fault(unsigned long address)
*/
#define SNP_FEATURES_IMPL (MSR_AMD64_SNP_DEBUG_SWAP | \
MSR_AMD64_SNP_SECURE_TSC | \
- SNP_FEATURE_SECURE_AVIC)
+ SNP_FEATURE_SECURE_AVIC | \
+ SNP_FEATURE_ALTERNATE_INJ)
u64 snp_get_unsupported_features(u64 status)
{
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread