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From: Reinette Chatre <reinette.chatre@intel.com>
To: Richard Cheng <icheng@nvidia.com>, <tony.luck@intel.com>,
	<shuah@kernel.org>, Ben Horgan <ben.horgan@arm.com>
Cc: <Dave.Martin@arm.com>, <james.morse@arm.com>,
	<babu.moger@amd.com>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>, <yu.c.chen@intel.com>,
	<fenghuay@nvidia.com>, <newtonl@nvidia.com>,
	<kristinc@nvidia.com>, <kaihengf@nvidia.com>, <kobak@nvidia.com>
Subject: Re: [PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64
Date: Thu, 25 Jun 2026 20:26:24 -0700	[thread overview]
Message-ID: <8d5a7235-f75c-4266-9deb-44465ff3fe42@intel.com> (raw)
In-Reply-To: <20260529022352.8308-3-icheng@nvidia.com>

+Ben

Hi Richard,

On 5/28/26 7:23 PM, Richard Cheng wrote:
> cl_flush() and sb() in fill_buf.c only have implementations for i386
> and x86_64, so on aarch64 both compile to empty functions. mem_flush()
> then walks the buffer calling a no-op cl_flush() per cache line and
> finishes with a no-op sb(), leaving any caller that expects a flushed
> buffer (e.g. CMT, L3_CAT) operating on unflushed state with no warning.
> 
> Add an aarch64 code block using the ARM equivalents:
> * "dc civac, %0" for cl_flush()
> * "dsb sy"       for sb()

Calling on Arm experts here since my superficial check found sfence to
be used for __wmb() on x86 and the Arm equivalent per
arch/arm64/include/asm/barrier.h appears to be "dsb st"?

Even so, it looks like the changes below were considered by Ben during
a previous submission but I am not able to tell if his feedback was taken
into account here.
Please see:
https://lore.kernel.org/lkml/4449219d-186f-4b5e-9f72-958d1af80f58@arm.com/
https://lore.kernel.org/lkml/5aea412c-9c7f-4692-af3e-79937956ef8c@arm.com/

> 
> Both instructions are EL0-accessible on Linux aarch64.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
>  tools/testing/selftests/resctrl/fill_buf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
> index 19a01a52dc1a..a41d21e5a64e 100644
> --- a/tools/testing/selftests/resctrl/fill_buf.c
> +++ b/tools/testing/selftests/resctrl/fill_buf.c
> @@ -27,6 +27,9 @@ static void sb(void)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("sfence\n\t"
>  		     : : : "memory");
> +#elif defined(__aarch64__)
> +	asm volatile("dsb sy\n\t"
> +		     : : : "memory");
>  #endif
>  }
>  
> @@ -35,6 +38,9 @@ static void cl_flush(void *p)
>  #if defined(__i386) || defined(__x86_64)
>  	asm volatile("clflush (%0)\n\t"
>  		     : : "r"(p) : "memory");
> +#elif defined(__aarch64__)
> +	asm volatile("dc civac, %0\n\t"
> +		     : : "r"(p) : "memory");
>  #endif
>  }
>  

Reinette

  reply	other threads:[~2026-06-26  3:26 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-29  2:23 [PATCH v3 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng
2026-05-29  2:23 ` [PATCH v3 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists Richard Cheng
2026-06-26  3:25   ` Reinette Chatre
2026-05-29  2:23 ` [PATCH v3 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64 Richard Cheng
2026-06-26  3:26   ` Reinette Chatre [this message]
2026-06-26 13:58     ` Ben Horgan
2026-07-02 14:15       ` Ben Horgan
2026-05-29  2:23 ` [PATCH v3 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT Richard Cheng
2026-05-31 19:01   ` Ilpo Järvinen
2026-06-26  3:26   ` Reinette Chatre
2026-05-29  2:28 ` [PATCH v3 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng

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