[PATCH v2 0/2] arm64: dts: qcom: sm8350: Add CPU capacities and power coefficients

[PATCH v2 0/2] arm64: dts: qcom: sm8350: Add CPU capacities and power coefficients

[Demeter Barna via B4 Relay]

Give the SM8350 CPUs their capacities and dynamic power coefficients, so
that the scheduler sees the three clusters as they are and energy aware
scheduling gets an energy model. Both come from Qualcomm's downstream
device trees.

Downstream, the capacities are the same for v1 and v2 silicon, but the
power coefficients are not: patch 2 takes the v2 ones, which the device
tested here (v2.1) carries too. I have no v1 part to check them on; if
v1 boards matter, patch 2 can wait without holding up patch 1.

Tested on a Razer Edge 5G (SM8350 v2.1), whose board support is not
upstream yet: cpu_capacity reads 308, 785 and 1024 once the kernel has
scaled the values by each cluster's maximum frequency (1804, 2419 and
2995 MHz), sched_energy_aware is 1, and the energy model covers all
three clusters. Compared with the same kernel without these patches, an
unpinned CPU-bound task now runs mostly on the X1 and a light periodic
task on the A55s. dtbs_check shows no new warning for the SM8350 boards.
The values come from Razer's kernel release for this device
(Nicole-msm-5.4.254-20240515).

---
Changes in v2:
- From and Signed-off-by now carry my real name instead of the handle
  "fromdisposition" used for v1 (same author). No code changes.
- Link to v1: https://patch.msgid.link/20261012-sm8350-cpu-capacity-v1-0-3d141e0099d5@fromdisposition.org

---
Demeter Barna (2):
      arm64: dts: qcom: sm8350: Add CPU capacities
      arm64: dts: qcom: sm8350: Add CPU dynamic power coefficients

 arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
---
base-commit: d053e38e614fb2e383b298ce8fc308a780d7f209
change-id: 20261012-sm8350-cpu-capacity-3145a6e159b3

Best regards,
--  
Demeter Barna <me@fromdisposition.org>

[PATCH v2 1/2] arm64: dts: qcom: sm8350: Add CPU capacities

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Without capacity-dmips-mhz every CPU reports a capacity of 1024, so the
scheduler treats the Cortex-A55, Cortex-A78 and Cortex-X1 cores as
equal and sets up no asymmetric CPU capacity.

Take the values from Qualcomm's downstream device tree for SM8350
(lahaina.dtsi in msm-5.4): 1024, 1946 and 2048, halved so that the X1 is
1024. Only their ratios matter, as the kernel normalizes them. The
downstream overlay for v2 silicon (lahaina-v2.dtsi) keeps them.

Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 55b32050c..df6e9d1fa 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -60,6 +60,7 @@ cpu0: cpu@0 {
 			reg = <0x0 0x0>;
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <512>;
 			next-level-cache = <&l2_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd0>;
@@ -84,6 +85,7 @@ cpu1: cpu@100 {
 			reg = <0x0 0x100>;
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <512>;
 			next-level-cache = <&l2_100>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd1>;
@@ -103,6 +105,7 @@ cpu2: cpu@200 {
 			reg = <0x0 0x200>;
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <512>;
 			next-level-cache = <&l2_200>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd2>;
@@ -122,6 +125,7 @@ cpu3: cpu@300 {
 			reg = <0x0 0x300>;
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <512>;
 			next-level-cache = <&l2_300>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd3>;
@@ -141,6 +145,7 @@ cpu4: cpu@400 {
 			reg = <0x0 0x400>;
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <973>;
 			next-level-cache = <&l2_400>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd4>;
@@ -160,6 +165,7 @@ cpu5: cpu@500 {
 			reg = <0x0 0x500>;
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <973>;
 			next-level-cache = <&l2_500>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd5>;
@@ -179,6 +185,7 @@ cpu6: cpu@600 {
 			reg = <0x0 0x600>;
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <973>;
 			next-level-cache = <&l2_600>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd6>;
@@ -198,6 +205,7 @@ cpu7: cpu@700 {
 			reg = <0x0 0x700>;
 			clocks = <&cpufreq_hw 2>;
 			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
 			next-level-cache = <&l2_700>;
 			qcom,freq-domain = <&cpufreq_hw 2>;
 			power-domains = <&cpu_pd7>;

-- 
2.53.0

Re: [PATCH v2 1/2] arm64: dts: qcom: sm8350: Add CPU capacities

[Konrad Dybcio]

On 10/12/26 5:56 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
> 
> Without capacity-dmips-mhz every CPU reports a capacity of 1024, so the
> scheduler treats the Cortex-A55, Cortex-A78 and Cortex-X1 cores as
> equal and sets up no asymmetric CPU capacity.
> 
> Take the values from Qualcomm's downstream device tree for SM8350
> (lahaina.dtsi in msm-5.4): 1024, 1946 and 2048, halved so that the X1 is
> 1024. Only their ratios matter, as the kernel normalizes them. The
> downstream overlay for v2 silicon (lahaina-v2.dtsi) keeps them.
> 
> Assisted-by: LLM
> Signed-off-by: Demeter Barna <me@fromdisposition.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 2/2] arm64: dts: qcom: sm8350: Add CPU dynamic power coefficients

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@fromdisposition.org>

Without dynamic-power-coefficient no energy model is registered for
these CPUs, so energy aware scheduling stays off.

Take the values from Qualcomm's downstream overlay for v2 silicon
(lahaina-v2.dtsi in msm-5.4): 100, 499 and 760 for the A55, A78 and X1.
For the A78 and the X1 it replaces the 515 and 845 of lahaina.dtsi.

Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index df6e9d1fa..dcd1fc9c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -61,6 +61,7 @@ cpu0: cpu@0 {
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <512>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd0>;
@@ -86,6 +87,7 @@ cpu1: cpu@100 {
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <512>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_100>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd1>;
@@ -106,6 +108,7 @@ cpu2: cpu@200 {
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <512>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_200>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd2>;
@@ -126,6 +129,7 @@ cpu3: cpu@300 {
 			clocks = <&cpufreq_hw 0>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <512>;
+			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_300>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			power-domains = <&cpu_pd3>;
@@ -146,6 +150,7 @@ cpu4: cpu@400 {
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <973>;
+			dynamic-power-coefficient = <499>;
 			next-level-cache = <&l2_400>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd4>;
@@ -166,6 +171,7 @@ cpu5: cpu@500 {
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <973>;
+			dynamic-power-coefficient = <499>;
 			next-level-cache = <&l2_500>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd5>;
@@ -186,6 +192,7 @@ cpu6: cpu@600 {
 			clocks = <&cpufreq_hw 1>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <973>;
+			dynamic-power-coefficient = <499>;
 			next-level-cache = <&l2_600>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			power-domains = <&cpu_pd6>;
@@ -206,6 +213,7 @@ cpu7: cpu@700 {
 			clocks = <&cpufreq_hw 2>;
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <760>;
 			next-level-cache = <&l2_700>;
 			qcom,freq-domain = <&cpufreq_hw 2>;
 			power-domains = <&cpu_pd7>;

-- 
2.53.0

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add CPU dynamic power coefficients

[Konrad Dybcio]

On 10/12/26 5:56 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
> 
> Without dynamic-power-coefficient no energy model is registered for
> these CPUs, so energy aware scheduling stays off.
> 
> Take the values from Qualcomm's downstream overlay for v2 silicon
> (lahaina-v2.dtsi in msm-5.4): 100, 499 and 760 for the A55, A78 and X1.
> For the A78 and the X1 it replaces the 515 and 845 of lahaina.dtsi.

I assume this mentions the diff vs the v1 chip. I find that a little
confusing to put in the commit message. FWIW if a v2 exists, v1 is
almost always internal-only and not of interest for upstream

in any case:

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad