Re: [PATCH v6 4/9] phy: rockchip-samsung-dcphy: Always write the rate-dependent registers

[Michael Riesch <michael.riesch@collabora.com>]

Hi Jason,

Thanks for the patch!

On 11/10/26 09:18, Jason Yang wrote:
> The lane timing init functions write DPHY_MC_ANA_CON1, the four data
> lane ANA_CON1 registers and DPHY_MC_DESKEW_CON0 only above a data
> rate threshold, and the registers have to be zero below it [1].
> 
> Today the APB reset at the start of every power_on provides the zero.
> 
> A later change moves that reset to runtime resume, so a power_on at a
> lower rate after a higher one would keep the old values.
> 
> Write the registers on every power_on, with zero below the threshold.
> 
> [1] RK3588 TRM: sections 22.4.2 (reset values) and 22.4.3
>     (DPHY_MC_ANA_CON1, DPHY_MC_DESKEW_CON0)
> 
> Signed-off-by: Jason Yang <jason98166@gmail.com>

Reviewed-by: Michael Riesch <michael.riesch@collabora.com>

Best regards,
Michael

> ---
>  drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 24 +++++++++++++++--------
>  1 file changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> index ce1bc62497c5..7a009d87a665 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> @@ -1228,7 +1228,10 @@ samsung_mipi_dphy_clk_lane_timing_init(struct samsung_mipi_dcphy *samsung)
>  	regmap_write(samsung->regmap, DPHY_MC_ANA_CON0, val);
>  
>  	if (lane_hs_rate >= 4500)
> -		regmap_write(samsung->regmap, DPHY_MC_ANA_CON1, 0x0001);
> +		val = 0x0001;
> +	else
> +		val = 0;
> +	regmap_write(samsung->regmap, DPHY_MC_ANA_CON1, val);
>  
>  	val = 0;
>  	/*
> @@ -1259,7 +1262,10 @@ samsung_mipi_dphy_clk_lane_timing_init(struct samsung_mipi_dcphy *samsung)
>  	 * under 1.5Gbps or equal to 1.5Gbps.
>  	 */
>  	if (lane_hs_rate > 1500)
> -		regmap_write(samsung->regmap, DPHY_MC_DESKEW_CON0, 0x9cb1);
> +		val = 0x9cb1;
> +	else
> +		val = 0;
> +	regmap_write(samsung->regmap, DPHY_MC_DESKEW_CON0, val);
>  }
>  
>  static void
> @@ -1284,12 +1290,14 @@ samsung_mipi_dphy_data_lane_timing_init(struct samsung_mipi_dcphy *samsung)
>  	regmap_write(samsung->regmap, COMBO_MD2_ANA_CON0, val);
>  	regmap_write(samsung->regmap, DPHY_MD3_ANA_CON0, val);
>  
> -	if (lane_hs_rate >= 4500) {
> -		regmap_write(samsung->regmap, COMBO_MD0_ANA_CON1, 0x0001);
> -		regmap_write(samsung->regmap, COMBO_MD1_ANA_CON1, 0x0001);
> -		regmap_write(samsung->regmap, COMBO_MD2_ANA_CON1, 0x0001);
> -		regmap_write(samsung->regmap, DPHY_MD3_ANA_CON1, 0x0001);
> -	}
> +	if (lane_hs_rate >= 4500)
> +		val = 0x0001;
> +	else
> +		val = 0;
> +	regmap_write(samsung->regmap, COMBO_MD0_ANA_CON1, val);
> +	regmap_write(samsung->regmap, COMBO_MD1_ANA_CON1, val);
> +	regmap_write(samsung->regmap, COMBO_MD2_ANA_CON1, val);
> +	regmap_write(samsung->regmap, DPHY_MD3_ANA_CON1, val);
>  
>  	val = 0;
>  	/*
>