mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Anup Patel" <apatel@ventanamicro.com>
Cc: "Atish Patra" <atish.patra@linux.dev>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Shuah Khan" <shuah@kernel.org>, <kvm@vger.kernel.org>,
	<kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 0/6] ONE_REG interface for SBI FWFT extension
Date: Tue, 19 Aug 2025 19:35:44 +0200	[thread overview]
Message-ID: <DC6L3PG5HP48.2J8TC1JZHMJVO@ventanamicro.com> (raw)
In-Reply-To: <CAK9=C2VA2jswYm_yxYsCaGKUkJT46rxUH-6OKdsApMZ8nhkrQw@mail.gmail.com>

2025-08-19T21:22:27+05:30, Anup Patel <apatel@ventanamicro.com>:
> On Tue, Aug 19, 2025 at 5:13 PM Radim Krčmář <rkrcmar@ventanamicro.com> wrote:
>>
>> 2025-08-19T12:00:43+05:30, Anup Patel <apatel@ventanamicro.com>:
>> > On Mon, Aug 18, 2025 at 3:59 PM Radim Krčmář <rkrcmar@ventanamicro.com> wrote:
>> >>
>> >> 2025-08-14T21:25:42+05:30, Anup Patel <apatel@ventanamicro.com>:
>> >> > This series adds ONE_REG interface for SBI FWFT extension implemented
>> >> > by KVM RISC-V.
>> >>
>> >> I think it would be better to ONE_REG the CSRs (medeleg/menvcfg), or at
>> >> least expose their CSR fields (each sensible medeleg bit, PMM, ...)
>> >> through kvm_riscv_config, than to couple this with SBI/FWFT.
>> >>
>> >> The controlled behavior is defined by the ISA, and userspace might want
>> >> to configure the S-mode execution environment even when SBI/FWFT is not
>> >> present, which is not possible with the current design.
>> >>
>> >> Is there a benefit in expressing the ISA model through SBI/FWFT?
>> >>
>> >
>> > Exposing medeleg/menvcfg is not the right approach because a
>> > Guest/VM does not have M-mode hence it is not appropriate to
>> > expose m<xyz> CSRs via ONE_REG interface. This also aligns
>> > with H-extension architecture which does not virtualize M-mode.
>>
>> We already have mvendorid, marchid, and mipid in kvm_riscv_config.
>
> The mvendorid, marchid, and mipid are accessible via SBI BASE
> extension but not any other M-mode CSRs hence these are special.
>
>>
>> The virtualized M-mode is userspace+KVM.  (KVM doesn't allow userspace
>> to configure most things now, but I think we'll have to change that when
>> getting ready for production.)
>
> The RISC-V architecture is not designed to virtualize M-mode
> and there is no practical use-case for virtualized M-mode hence
> WE WON'T BE SUPPORTING IT IN KVM RISC-V.

Oh, sorry for the misunderstanding, I'll be clearer next time and talk
about implementation of the supervisor execution environment.
KVM+userspace provides SEE to the VS-mode, which is to VS-mode as what
M-mode is to S-mode, hence I called KVM+userspace a virtualized M-mode.

> FYI, the KVM ARM64 does not virtualize EL3 either and it is
> already in production so please stop making random arguments
> for requiring virtualized M-mode for production.

Yeah, I agree that we don't need it, I just had to provide so many
examples in the previous discussion that I went into quite niche cases.

The increased flexibility is similarly useful for more important cases:
we can't avoid "virtualized M-mode"/SEE, but we don't have to completely
implement it in HS-mode.

>> For general virtualization, we want to be able to configure the
>> following behavior for each exception that would go to the virtualized
>> M-mode:
>>   0) delegated to the guest
>>   1) implemented by userspace
>>   2-N) implementations by KVM (ideally zero or one)
>>
>> We can have medeleg, and another method to decide how to handle trapped
>> exceptions, but it probably makes more sense to have a per-exception
>> ONE_REG that sets how each exception behaves.
>>
>
> No pointing in discussing this further since we won't be supporting
> virtualized M-mode.

I understand, back to the current series:

I think we need to provide means with which userspace can control which
FWFT features are enabled, because KVM just exposes everything it know
and hardware supports right now:
 1) Migration between different systems would be hindered
 2) We couldn't add more FWFT features without breaking the SEE

The (2) is similar to how we must set ".default_disabled = true" to
current FWFT, because KVM can't be changing the SEE for userspace.

Do you want me to send a patch that inverts the default, to make all
future SBI extension start as disabled, so we can't easily repeat the
mistake in the future?

Thanks.

  reply	other threads:[~2025-08-19 17:35 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-14 15:55 Anup Patel
2025-08-14 15:55 ` [PATCH 1/6] RISC-V: KVM: Set initial value of hedeleg in kvm_arch_vcpu_create() Anup Patel
2025-08-15 20:04   ` Andrew Jones
2025-08-19  9:01   ` Nutty.Liu
2025-08-14 15:55 ` [PATCH 2/6] RISC-V: KVM: Introduce feature specific reset for SBI FWFT Anup Patel
2025-08-15 20:14   ` Andrew Jones
2025-08-19  9:02   ` Nutty.Liu
2025-08-14 15:55 ` [PATCH 3/6] RISC-V: KVM: Introduce optional ONE_REG callbacks for SBI extensions Anup Patel
2025-08-15 21:00   ` Andrew Jones
2025-08-17 12:04     ` Anup Patel
2025-08-14 15:55 ` [PATCH 4/6] RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation Anup Patel
2025-08-15 21:04   ` Andrew Jones
2025-08-14 15:55 ` [PATCH 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Anup Patel
2025-08-14 15:55 ` [PATCH 6/6] KVM: riscv: selftests: Add SBI FWFT to get-reg-list test Anup Patel
2025-08-18 10:29 ` [PATCH 0/6] ONE_REG interface for SBI FWFT extension Radim Krčmář
2025-08-19  6:30   ` Anup Patel
2025-08-19 11:43     ` Radim Krčmář
2025-08-19 15:52       ` Anup Patel
2025-08-19 17:35         ` Radim Krčmář [this message]
2025-08-21  6:26           ` Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DC6L3PG5HP48.2J8TC1JZHMJVO@ventanamicro.com \
    --to=rkrcmar@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=alex@ghiti.fr \
    --cc=anup@brainfault.org \
    --cc=apatel@ventanamicro.com \
    --cc=atish.patra@linux.dev \
    --cc=kvm-riscv@lists.infradead.org \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-kselftest@vger.kernel.org \
    --cc=linux-riscv-bounces@lists.infradead.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=pbonzini@redhat.com \
    --cc=shuah@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®