From: "Gary Guo" <gary@garyguo.net>
To: "Philipp Stanner" <phasta@kernel.org>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
"Yury Norov" <yury.norov@gmail.com>,
"Rasmus Villemoes" <linux@rasmusvillemoes.dk>,
"Arnd Bergmann" <arnd@arndb.de>,
"Tvrtko Ursulin" <tvrtko.ursulin@igalia.com>,
"Danilo Krummrich" <dakr@kernel.org>,
"Gary Guo" <gary@garyguo.net>,
"Paul E . McKenney" <paulmck@kernel.org>
Cc: <linux-media@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>
Subject: Re: [PATCH 1/2] asm-generic/bitops: Add set_bit_release()
Date: Wed, 21 Oct 2026 13:06:47 +0100 [thread overview]
Message-ID: <DMAI50AJ10UC.16G4TCC3VAM0J@garyguo.net> (raw)
In-Reply-To: <20261021095512.1345191-3-phasta@kernel.org>
On Wed Oct 21, 2026 at 10:55 AM BST, Philipp Stanner wrote:
> The kernel already has test_bit_acquire(). A set_bit_release(), however,
> was missing so far. It can be expected to be useful for parties that
> need release ordering, but not the stricter full ordering of the other
> bit-setting functions.
>
> Add set_bit_release().
>
> Signed-off-by: Philipp Stanner <phasta@kernel.org>
> ---
> include/asm-generic/bitops/instrumented-atomic.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/include/asm-generic/bitops/instrumented-atomic.h b/include/asm-generic/bitops/instrumented-atomic.h
> index c010d54275e4..fb2d1472fd4d 100644
> --- a/include/asm-generic/bitops/instrumented-atomic.h
> +++ b/include/asm-generic/bitops/instrumented-atomic.h
> @@ -72,6 +72,20 @@ static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *ad
> return arch_test_and_set_bit(nr, addr);
> }
>
> +/**
> + * set_bit_release - Set a bit with release ordering
> + * @nr: Bit to set
> + * @addr: Address to start counting from
> + *
> + * This is an atomic ordered operation (implied write memory barrier).
> + */
> +static __always_inline void set_bit_release(long nr, volatile unsigned long *addr)
> +{
> + kcsan_wmb();
> + instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long));
> + arch_set_bit(nr, addr);
This is just wrong. There's no code here that gives you the release semantics.
kcsan_wmb() is just an annotation and does nothing. wmb is also not release
semantics as it does not order LOAD->STORE.
Given that set_bit is a relaxed RMW atomic, you can implement set_bit_release
with just
smp_mb__before_atomic();
set_bit(nr, addr);
Which should be correct, but is too strong on some architectures (like RISC-V),
becuase it will produce a full MB instead. So we can either add release barriers
(hint: I really like it), or we can add arch_set_bit_release and implement it
per arch; on RISC-V for example it can then be translated to amoor.rl (which is
not being produced by any existing bit ops).c
Best,
Gary
> +}
> +
> /**
> * test_and_clear_bit - Clear a bit and return its old value
> * @nr: Bit to clear
next prev parent reply other threads:[~2026-10-21 12:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 9:55 [PATCH 0/2] dma-fence: Order is-signaled-bit Philipp Stanner
2026-10-21 9:55 ` [PATCH 1/2] asm-generic/bitops: Add set_bit_release() Philipp Stanner
2026-10-21 11:33 ` Arnd Bergmann
2026-10-21 11:54 ` Gary Guo
2026-10-21 12:15 ` Arnd Bergmann
2026-10-21 12:06 ` Gary Guo [this message]
2026-10-21 12:17 ` Philipp Stanner
2026-10-21 12:24 ` Gary Guo
2026-10-21 13:22 ` Philipp Stanner
2026-10-21 9:55 ` [PATCH 2/2] dma-buf/dma-fence: Order setting of the signaled-bit properly Philipp Stanner
2026-10-21 13:47 ` Christian König
2026-10-21 14:52 ` Philipp Stanner
2026-10-21 15:04 ` Christian König
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