* [PATCH v1 01/31] tty: mxser: serial: 8250: replace mxser with 8250-based driver
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:07 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 02/31] serial: 8250: add MU860 UART configuration Crescent Hsieh
` (29 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Remove the legacy mxser driver and replace it with 8250-based
implementation (8250_mxupci) for Moxa UPCI serial devices.
This simplifies maintenance and improves integration with the existing
8250 serial infrastructure.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/Kconfig | 13 -
drivers/tty/Makefile | 1 -
drivers/tty/mxser.c | 1934 -------------------------
drivers/tty/serial/8250/8250_mxupci.c | 165 +++
drivers/tty/serial/8250/Kconfig | 11 +
drivers/tty/serial/8250/Makefile | 1 +
6 files changed, 177 insertions(+), 1948 deletions(-)
delete mode 100644 drivers/tty/mxser.c
create mode 100644 drivers/tty/serial/8250/8250_mxupci.c
diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig
index 63a494d36a1f..3973b52bcfce 100644
--- a/drivers/tty/Kconfig
+++ b/drivers/tty/Kconfig
@@ -218,19 +218,6 @@ config MOXA_INTELLIO
To compile this driver as a module, choose M here: the
module will be called moxa.
-config MOXA_SMARTIO
- tristate "Moxa SmartIO support v. 2.0"
- depends on SERIAL_NONSTANDARD && PCI && HAS_IOPORT
- help
- Say Y here if you have a Moxa SmartIO multiport serial card and/or
- want to help develop a new version of this driver.
-
- This is upgraded (1.9.1) driver from original Moxa drivers with
- changes finally resulting in PCI probing.
-
- This driver can also be built as a module. The module will be called
- mxser. If you want to do that, say M here.
-
config SYNCLINK_GT
tristate "SyncLink GT/AC support"
depends on SERIAL_NONSTANDARD && PCI
diff --git a/drivers/tty/Makefile b/drivers/tty/Makefile
index 07aca5184a55..7db70532e8da 100644
--- a/drivers/tty/Makefile
+++ b/drivers/tty/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_SERIAL_DEV_BUS) += serdev/
# tty drivers
obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
-obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
obj-$(CONFIG_NOZOMI) += nozomi.o
obj-$(CONFIG_NULL_TTY) += ttynull.o
obj-$(CONFIG_SYNCLINK_GT) += synclink_gt.o
diff --git a/drivers/tty/mxser.c b/drivers/tty/mxser.c
deleted file mode 100644
index 4d45eca4929a..000000000000
--- a/drivers/tty/mxser.c
+++ /dev/null
@@ -1,1934 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
- *
- * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
- * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
- *
- * This code is loosely based on the 1.8 moxa driver which is based on
- * Linux serial driver, written by Linus Torvalds, Theodore T'so and
- * others.
- *
- * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
- * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
- * www.moxa.com.
- * - Fixed x86_64 cleanness
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/serial.h>
-#include <linux/serial_reg.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/pci.h>
-#include <linux/bitops.h>
-#include <linux/slab.h>
-#include <linux/ratelimit.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <linux/uaccess.h>
-
-/*
- * Semi-public control interfaces
- */
-
-/*
- * MOXA ioctls
- */
-
-#define MOXA 0x400
-#define MOXA_SET_OP_MODE (MOXA + 66)
-#define MOXA_GET_OP_MODE (MOXA + 67)
-
-#define RS232_MODE 0
-#define RS485_2WIRE_MODE 1
-#define RS422_MODE 2
-#define RS485_4WIRE_MODE 3
-#define OP_MODE_MASK 3
-
-/* --------------------------------------------------- */
-
-/*
- * Follow just what Moxa Must chip defines.
- *
- * When LCR register (offset 0x03) is written the following value, the Must chip
- * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
- * change bank.
- */
-#define MOXA_MUST_ENTER_ENHANCED 0xBF
-
-/* when enhanced mode is enabled, access to general bank register */
-#define MOXA_MUST_GDL_REGISTER 0x07
-#define MOXA_MUST_GDL_MASK 0x7F
-#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
-
-#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
-/* enhanced register bank select and enhanced mode setting register */
-/* This works only when LCR register equals to 0xBF */
-#define MOXA_MUST_EFR_REGISTER 0x02
-#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
-/* enhanced register bank set 0, 1, 2 */
-#define MOXA_MUST_EFR_BANK0 0x00
-#define MOXA_MUST_EFR_BANK1 0x40
-#define MOXA_MUST_EFR_BANK2 0x80
-#define MOXA_MUST_EFR_BANK3 0xC0
-#define MOXA_MUST_EFR_BANK_MASK 0xC0
-
-/* set XON1 value register, when LCR=0xBF and change to bank0 */
-#define MOXA_MUST_XON1_REGISTER 0x04
-
-/* set XON2 value register, when LCR=0xBF and change to bank0 */
-#define MOXA_MUST_XON2_REGISTER 0x05
-
-/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
-#define MOXA_MUST_XOFF1_REGISTER 0x06
-
-/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
-#define MOXA_MUST_XOFF2_REGISTER 0x07
-
-#define MOXA_MUST_RBRTL_REGISTER 0x04
-#define MOXA_MUST_RBRTH_REGISTER 0x05
-#define MOXA_MUST_RBRTI_REGISTER 0x06
-#define MOXA_MUST_THRTL_REGISTER 0x07
-#define MOXA_MUST_ENUM_REGISTER 0x04
-#define MOXA_MUST_HWID_REGISTER 0x05
-#define MOXA_MUST_ECR_REGISTER 0x06
-#define MOXA_MUST_CSR_REGISTER 0x07
-
-#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
-#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
-
-#define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
-#define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
-#define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
-#define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
-
-#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
-
-/* GDA interrupt pending */
-#define MOXA_MUST_IIR_GDA 0x1C
-#define MOXA_MUST_IIR_RDA 0x04
-#define MOXA_MUST_IIR_RTO 0x0C
-#define MOXA_MUST_IIR_LSR 0x06
-
-/* received Xon/Xoff or specical interrupt pending */
-#define MOXA_MUST_IIR_XSC 0x10
-
-/* RTS/CTS change state interrupt pending */
-#define MOXA_MUST_IIR_RTSCTS 0x20
-#define MOXA_MUST_IIR_MASK 0x3E
-
-#define MOXA_MUST_MCR_XON_FLAG 0x40
-#define MOXA_MUST_MCR_XON_ANY 0x80
-#define MOXA_MUST_MCR_TX_XON 0x08
-
-#define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
-#define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
-#define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
-#define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
-#define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
-#define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
-#define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
-#define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
-#define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
-#define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
-#define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
-
-#define MXSERMAJOR 174
-
-#define MXSER_BOARDS 4 /* Max. boards */
-#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
-#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
-#define MXSER_ISR_PASS_LIMIT 100
-
-#define WAKEUP_CHARS 256
-
-#define MXSER_BAUD_BASE 921600
-#define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
-
-#define PCI_DEVICE_ID_MOXA_RC7000 0x0001
-#define PCI_DEVICE_ID_MOXA_CP102 0x1020
-#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
-#define PCI_DEVICE_ID_MOXA_CP102U 0x1022
-#define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
-#define PCI_DEVICE_ID_MOXA_C104 0x1040
-#define PCI_DEVICE_ID_MOXA_CP104U 0x1041
-#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
-#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
-#define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
-#define PCI_DEVICE_ID_MOXA_CB108 0x1080
-#define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
-#define PCI_DEVICE_ID_MOXA_CT114 0x1140
-#define PCI_DEVICE_ID_MOXA_CP114 0x1141
-#define PCI_DEVICE_ID_MOXA_CB114 0x1142
-#define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
-#define PCI_DEVICE_ID_MOXA_CP118U 0x1180
-#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
-#define PCI_DEVICE_ID_MOXA_CP132 0x1320
-#define PCI_DEVICE_ID_MOXA_CP132U 0x1321
-#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
-#define PCI_DEVICE_ID_MOXA_CB134I 0x1341
-#define PCI_DEVICE_ID_MOXA_CP138U 0x1380
-#define PCI_DEVICE_ID_MOXA_C168 0x1680
-#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
-#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
-
-#define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
-#define MXSER_HIGHBAUD 0x0100
-
-enum mxser_must_hwid {
- MOXA_OTHER_UART = 0x00,
- MOXA_MUST_MU150_HWID = 0x01,
- MOXA_MUST_MU860_HWID = 0x02,
-};
-
-static const struct {
- u8 type;
- u8 fifo_size;
- u8 rx_high_water;
- u8 rx_low_water;
- speed_t max_baud;
-} Gpci_uart_info[] = {
- { MOXA_OTHER_UART, 16, 14, 1, 921600 },
- { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
- { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
-};
-#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
-
-static const struct pci_device_id mxser_pcibrds[] = {
- { PCI_DEVICE_DATA(MOXA, C168, 8) },
- { PCI_DEVICE_DATA(MOXA, C104, 4) },
- { PCI_DEVICE_DATA(MOXA, CP132, 2) },
- { PCI_DEVICE_DATA(MOXA, CP114, 4) },
- { PCI_DEVICE_DATA(MOXA, CT114, 4) },
- { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) },
- { PCI_DEVICE_DATA(MOXA, CP104U, 4) },
- { PCI_DEVICE_DATA(MOXA, CP168U, 8) },
- { PCI_DEVICE_DATA(MOXA, CP132U, 2) },
- { PCI_DEVICE_DATA(MOXA, CP134U, 4) },
- { PCI_DEVICE_DATA(MOXA, CP104JU, 4) },
- { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */
- { PCI_DEVICE_DATA(MOXA, CP118U, 8) },
- { PCI_DEVICE_DATA(MOXA, CP102UL, 2) },
- { PCI_DEVICE_DATA(MOXA, CP102U, 2) },
- { PCI_DEVICE_DATA(MOXA, CP118EL, 8) },
- { PCI_DEVICE_DATA(MOXA, CP168EL, 8) },
- { PCI_DEVICE_DATA(MOXA, CP104EL, 4) },
- { PCI_DEVICE_DATA(MOXA, CB108, 8) },
- { PCI_DEVICE_DATA(MOXA, CB114, 4) },
- { PCI_DEVICE_DATA(MOXA, CB134I, 4) },
- { PCI_DEVICE_DATA(MOXA, CP138U, 8) },
- { PCI_DEVICE_DATA(MOXA, POS104UL, 4) },
- { PCI_DEVICE_DATA(MOXA, CP114UL, 4) },
- { PCI_DEVICE_DATA(MOXA, CP102UF, 2) },
- { PCI_DEVICE_DATA(MOXA, CP112UL, 2) },
- { }
-};
-MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
-
-static int ttymajor = MXSERMAJOR;
-
-/* Variables for insmod */
-
-MODULE_AUTHOR("Casper Yang");
-MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
-module_param(ttymajor, int, 0);
-MODULE_LICENSE("GPL");
-
-struct mxser_board;
-
-struct mxser_port {
- struct tty_port port;
- struct mxser_board *board;
-
- unsigned long ioaddr;
- unsigned long opmode_ioaddr;
-
- u8 rx_high_water;
- u8 rx_low_water;
- int type; /* UART type */
-
- u8 x_char; /* xon/xoff character */
- u8 IER; /* Interrupt Enable Register */
- u8 MCR; /* Modem control register */
- u8 FCR; /* FIFO control register */
-
- struct async_icount icount; /* kernel counters for 4 input interrupts */
- unsigned int timeout;
-
- u8 read_status_mask;
- u8 ignore_status_mask;
- u8 xmit_fifo_size;
-
- spinlock_t slock;
-};
-
-struct mxser_board {
- unsigned int idx;
- unsigned short nports;
- int irq;
- unsigned long vector;
-
- enum mxser_must_hwid must_hwid;
- speed_t max_baud;
-
- struct mxser_port ports[] /* __counted_by(nports) */;
-};
-
-static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
-static struct tty_driver *mxvar_sdriver;
-
-static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
- bool restore_LCR)
-{
- u8 oldlcr, efr;
-
- oldlcr = inb(baseio + UART_LCR);
- outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
-
- efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
- efr &= ~clear;
- efr |= set;
-
- outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
-
- if (restore_LCR)
- outb(oldlcr, baseio + UART_LCR);
-
- return oldlcr;
-}
-
-static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
-{
- return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
- false);
-}
-
-static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
-{
- u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
- outb(value, baseio + MOXA_MUST_XON1_REGISTER);
- outb(oldlcr, baseio + UART_LCR);
-}
-
-static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
-{
- u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
- outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
- outb(oldlcr, baseio + UART_LCR);
-}
-
-static void mxser_set_must_fifo_value(struct mxser_port *info)
-{
- u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
- outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
- outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
- outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
- outb(oldlcr, info->ioaddr + UART_LCR);
-}
-
-static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
-{
- u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
- outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
- outb(oldlcr, baseio + UART_LCR);
-}
-
-static u8 mxser_get_must_hardware_id(unsigned long baseio)
-{
- u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
- u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
- outb(oldlcr, baseio + UART_LCR);
-
- return id;
-}
-
-static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
-{
- __mxser_must_set_EFR(baseio, clear, set, true);
-}
-
-static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
-{
- mxser_must_set_EFR(baseio,
- enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
- enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
-}
-
-static void mxser_must_no_sw_flow_control(unsigned long baseio)
-{
- mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
-}
-
-static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
-{
- mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
- enable ? MOXA_MUST_EFR_SF_TX1 : 0);
-}
-
-static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
-{
- mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
- enable ? MOXA_MUST_EFR_SF_RX1 : 0);
-}
-
-static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
-{
- u8 oldmcr, hwid;
- int i;
-
- outb(0, io + UART_LCR);
- mxser_must_set_enhance_mode(io, false);
- oldmcr = inb(io + UART_MCR);
- outb(0, io + UART_MCR);
- mxser_set_must_xon1_value(io, 0x11);
- if (inb(io + UART_MCR) != 0) {
- outb(oldmcr, io + UART_MCR);
- return MOXA_OTHER_UART;
- }
-
- hwid = mxser_get_must_hardware_id(io);
- for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
- if (hwid == Gpci_uart_info[i].type)
- return hwid;
-
- return MOXA_OTHER_UART;
-}
-
-static bool mxser_16550A_or_MUST(struct mxser_port *info)
-{
- return info->type == PORT_16550A || info->board->must_hwid;
-}
-
-static void mxser_process_txrx_fifo(struct mxser_port *info)
-{
- unsigned int i;
-
- if (info->type == PORT_16450 || info->type == PORT_8250) {
- info->rx_high_water = 1;
- info->rx_low_water = 1;
- info->xmit_fifo_size = 1;
- return;
- }
-
- for (i = 0; i < UART_INFO_NUM; i++)
- if (info->board->must_hwid == Gpci_uart_info[i].type) {
- info->rx_low_water = Gpci_uart_info[i].rx_low_water;
- info->rx_high_water = Gpci_uart_info[i].rx_high_water;
- info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
- break;
- }
-}
-
-static void __mxser_start_tx(struct mxser_port *info)
-{
- outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
- info->IER |= UART_IER_THRI;
- outb(info->IER, info->ioaddr + UART_IER);
-}
-
-static void mxser_start_tx(struct mxser_port *info)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- __mxser_start_tx(info);
- spin_unlock_irqrestore(&info->slock, flags);
-}
-
-static void __mxser_stop_tx(struct mxser_port *info)
-{
- info->IER &= ~UART_IER_THRI;
- outb(info->IER, info->ioaddr + UART_IER);
-}
-
-static bool mxser_carrier_raised(struct tty_port *port)
-{
- struct mxser_port *mp = container_of(port, struct mxser_port, port);
-
- return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD;
-}
-
-static void mxser_dtr_rts(struct tty_port *port, bool active)
-{
- struct mxser_port *mp = container_of(port, struct mxser_port, port);
- unsigned long flags;
- u8 mcr;
-
- spin_lock_irqsave(&mp->slock, flags);
- mcr = inb(mp->ioaddr + UART_MCR);
- if (active)
- mcr |= UART_MCR_DTR | UART_MCR_RTS;
- else
- mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
- outb(mcr, mp->ioaddr + UART_MCR);
- spin_unlock_irqrestore(&mp->slock, flags);
-}
-
-static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned int quot = 0, baud;
- unsigned char cval;
- u64 timeout;
-
- if (newspd > info->board->max_baud)
- return -1;
-
- if (newspd == 134) {
- quot = 2 * MXSER_BAUD_BASE / 269;
- tty_encode_baud_rate(tty, 134, 134);
- } else if (newspd) {
- quot = MXSER_BAUD_BASE / newspd;
- if (quot == 0)
- quot = 1;
- baud = MXSER_BAUD_BASE / quot;
- tty_encode_baud_rate(tty, baud, baud);
- } else {
- quot = 0;
- }
-
- /*
- * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
- * u64 domain
- */
- timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
- do_div(timeout, MXSER_BAUD_BASE);
- info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
-
- if (quot) {
- info->MCR |= UART_MCR_DTR;
- outb(info->MCR, info->ioaddr + UART_MCR);
- } else {
- info->MCR &= ~UART_MCR_DTR;
- outb(info->MCR, info->ioaddr + UART_MCR);
- return 0;
- }
-
- cval = inb(info->ioaddr + UART_LCR);
-
- outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
-
- outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
- outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
- outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
-
- if (C_BAUD(tty) == BOTHER) {
- quot = MXSER_BAUD_BASE % newspd;
- quot *= 8;
- if (quot % newspd > newspd / 2) {
- quot /= newspd;
- quot++;
- } else
- quot /= newspd;
-
- mxser_set_must_enum_value(info->ioaddr, quot);
- } else {
- mxser_set_must_enum_value(info->ioaddr, 0);
- }
-
- return 0;
-}
-
-static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
- u8 msr)
-{
- bool cts = msr & UART_MSR_CTS;
-
- if (tty->hw_stopped) {
- if (cts) {
- tty->hw_stopped = false;
-
- if (!mxser_16550A_or_MUST(info))
- __mxser_start_tx(info);
- tty_wakeup(tty);
- }
- return;
- } else if (cts)
- return;
-
- tty->hw_stopped = true;
- if (!mxser_16550A_or_MUST(info))
- __mxser_stop_tx(info);
-}
-
-/*
- * This routine is called to set the UART divisor registers to match
- * the specified baud rate for a serial port.
- */
-static void mxser_change_speed(struct tty_struct *tty,
- const struct ktermios *old_termios)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned cflag, cval;
-
- cflag = tty->termios.c_cflag;
-
- if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
- /* Use previous rate on a failure */
- if (old_termios) {
- speed_t baud = tty_termios_baud_rate(old_termios);
- tty_encode_baud_rate(tty, baud, baud);
- }
- }
-
- /* byte size and parity */
- cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
-
- if (cflag & CSTOPB)
- cval |= UART_LCR_STOP;
- if (cflag & PARENB)
- cval |= UART_LCR_PARITY;
- if (!(cflag & PARODD))
- cval |= UART_LCR_EPAR;
- if (cflag & CMSPAR)
- cval |= UART_LCR_SPAR;
-
- info->FCR = 0;
- if (info->board->must_hwid) {
- info->FCR |= UART_FCR_ENABLE_FIFO |
- MOXA_MUST_FCR_GDA_MODE_ENABLE;
- mxser_set_must_fifo_value(info);
- } else if (info->type != PORT_8250 && info->type != PORT_16450) {
- info->FCR |= UART_FCR_ENABLE_FIFO;
- switch (info->rx_high_water) {
- case 1:
- info->FCR |= UART_FCR_TRIGGER_1;
- break;
- case 4:
- info->FCR |= UART_FCR_TRIGGER_4;
- break;
- case 8:
- info->FCR |= UART_FCR_TRIGGER_8;
- break;
- default:
- info->FCR |= UART_FCR_TRIGGER_14;
- break;
- }
- }
-
- /* CTS flow control flag and modem status interrupts */
- info->IER &= ~UART_IER_MSI;
- info->MCR &= ~UART_MCR_AFE;
- tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
- if (cflag & CRTSCTS) {
- info->IER |= UART_IER_MSI;
- if (mxser_16550A_or_MUST(info)) {
- info->MCR |= UART_MCR_AFE;
- } else {
- mxser_handle_cts(tty, info,
- inb(info->ioaddr + UART_MSR));
- }
- }
- outb(info->MCR, info->ioaddr + UART_MCR);
- tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
- if (~cflag & CLOCAL)
- info->IER |= UART_IER_MSI;
- outb(info->IER, info->ioaddr + UART_IER);
-
- /*
- * Set up parity check flag
- */
- info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
- if (I_INPCK(tty))
- info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
- if (I_BRKINT(tty) || I_PARMRK(tty))
- info->read_status_mask |= UART_LSR_BI;
-
- info->ignore_status_mask = 0;
-
- if (I_IGNBRK(tty)) {
- info->ignore_status_mask |= UART_LSR_BI;
- info->read_status_mask |= UART_LSR_BI;
- /*
- * If we're ignore parity and break indicators, ignore
- * overruns too. (For real raw support).
- */
- if (I_IGNPAR(tty)) {
- info->ignore_status_mask |=
- UART_LSR_OE |
- UART_LSR_PE |
- UART_LSR_FE;
- info->read_status_mask |=
- UART_LSR_OE |
- UART_LSR_PE |
- UART_LSR_FE;
- }
- }
- if (info->board->must_hwid) {
- mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
- mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
- mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
- mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
- }
-
-
- outb(info->FCR, info->ioaddr + UART_FCR);
- outb(cval, info->ioaddr + UART_LCR);
-}
-
-static u8 mxser_check_modem_status(struct tty_struct *tty,
- struct mxser_port *port)
-{
- u8 msr = inb(port->ioaddr + UART_MSR);
-
- if (!(msr & UART_MSR_ANY_DELTA))
- return msr;
-
- /* update input line counters */
- if (msr & UART_MSR_TERI)
- port->icount.rng++;
- if (msr & UART_MSR_DDSR)
- port->icount.dsr++;
- if (msr & UART_MSR_DDCD)
- port->icount.dcd++;
- if (msr & UART_MSR_DCTS)
- port->icount.cts++;
- wake_up_interruptible(&port->port.delta_msr_wait);
-
- if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
- if (msr & UART_MSR_DCD)
- wake_up_interruptible(&port->port.open_wait);
- }
-
- if (tty_port_cts_enabled(&port->port))
- mxser_handle_cts(tty, port, msr);
-
- return msr;
-}
-
-static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
-{
- u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
-
- if (info->board->must_hwid)
- fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
-
- outb(fcr, info->ioaddr + UART_FCR);
-}
-
-static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
-{
- struct mxser_port *info = container_of(port, struct mxser_port, port);
- unsigned long flags;
- int ret;
-
- ret = tty_port_alloc_xmit_buf(port);
- if (ret < 0)
- return ret;
-
- spin_lock_irqsave(&info->slock, flags);
-
- if (!info->type) {
- set_bit(TTY_IO_ERROR, &tty->flags);
- spin_unlock_irqrestore(&info->slock, flags);
- ret = 0;
- goto err_free_xmit;
- }
-
- /*
- * Clear the FIFO buffers and disable them
- * (they will be reenabled in mxser_change_speed())
- */
- mxser_disable_and_clear_FIFO(info);
-
- /*
- * At this point there's no way the LSR could still be 0xFF;
- * if it is, then bail out, because there's likely no UART
- * here.
- */
- if (inb(info->ioaddr + UART_LSR) == 0xff) {
- spin_unlock_irqrestore(&info->slock, flags);
- if (capable(CAP_SYS_ADMIN)) {
- set_bit(TTY_IO_ERROR, &tty->flags);
- return 0;
- }
-
- ret = -ENODEV;
- goto err_free_xmit;
- }
-
- /*
- * Clear the interrupt registers.
- */
- (void) inb(info->ioaddr + UART_LSR);
- (void) inb(info->ioaddr + UART_RX);
- (void) inb(info->ioaddr + UART_IIR);
- (void) inb(info->ioaddr + UART_MSR);
-
- /*
- * Now, initialize the UART
- */
- outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
- info->MCR = UART_MCR_DTR | UART_MCR_RTS;
- outb(info->MCR, info->ioaddr + UART_MCR);
-
- /*
- * Finally, enable interrupts
- */
- info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
-
- if (info->board->must_hwid)
- info->IER |= MOXA_MUST_IER_EGDAI;
- outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
-
- /*
- * And clear the interrupt registers again for luck.
- */
- (void) inb(info->ioaddr + UART_LSR);
- (void) inb(info->ioaddr + UART_RX);
- (void) inb(info->ioaddr + UART_IIR);
- (void) inb(info->ioaddr + UART_MSR);
-
- clear_bit(TTY_IO_ERROR, &tty->flags);
- kfifo_reset(&port->xmit_fifo);
-
- /*
- * and set the speed of the serial port
- */
- mxser_change_speed(tty, NULL);
- spin_unlock_irqrestore(&info->slock, flags);
-
- return 0;
-err_free_xmit:
- tty_port_free_xmit_buf(port);
- return ret;
-}
-
-/*
- * To stop accepting input, we disable the receive line status interrupts, and
- * tell the interrupt driver to stop checking the data ready bit in the line
- * status register.
- */
-static void mxser_stop_rx(struct mxser_port *info)
-{
- info->IER &= ~UART_IER_RLSI;
- if (info->board->must_hwid)
- info->IER &= ~MOXA_MUST_RECV_ISR;
-
- outb(info->IER, info->ioaddr + UART_IER);
-}
-
-/*
- * This routine will shutdown a serial port
- */
-static void mxser_shutdown_port(struct tty_port *port)
-{
- struct mxser_port *info = container_of(port, struct mxser_port, port);
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
-
- mxser_stop_rx(info);
-
- /*
- * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
- * here so the queue might never be waken up
- */
- wake_up_interruptible(&info->port.delta_msr_wait);
-
- info->IER = 0;
- outb(0x00, info->ioaddr + UART_IER);
-
- /* clear Rx/Tx FIFO's */
- mxser_disable_and_clear_FIFO(info);
-
- /* read data port to reset things */
- (void) inb(info->ioaddr + UART_RX);
-
-
- if (info->board->must_hwid)
- mxser_must_no_sw_flow_control(info->ioaddr);
-
- spin_unlock_irqrestore(&info->slock, flags);
-
- /* make sure ISR is not running while we free the buffer */
- synchronize_irq(info->board->irq);
-
- tty_port_free_xmit_buf(port);
-}
-
-/*
- * This routine is called whenever a serial port is opened. It
- * enables interrupts for a serial port, linking in its async structure into
- * the IRQ chain. It also performs the serial-specific
- * initialization for the tty structure.
- */
-static int mxser_open(struct tty_struct *tty, struct file *filp)
-{
- struct tty_port *tport = tty->port;
- struct mxser_port *port = container_of(tport, struct mxser_port, port);
-
- tty->driver_data = port;
-
- return tty_port_open(tport, tty, filp);
-}
-
-static void mxser_flush_buffer(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- kfifo_reset(&info->port.xmit_fifo);
-
- outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
- info->ioaddr + UART_FCR);
-
- spin_unlock_irqrestore(&info->slock, flags);
-
- tty_wakeup(tty);
-}
-
-static void mxser_close(struct tty_struct *tty, struct file *filp)
-{
- tty_port_close(tty->port, tty, filp);
-}
-
-static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
- size_t written;
- bool is_empty;
-
- spin_lock_irqsave(&info->slock, flags);
- written = kfifo_in(&info->port.xmit_fifo, buf, count);
- is_empty = kfifo_is_empty(&info->port.xmit_fifo);
- spin_unlock_irqrestore(&info->slock, flags);
-
- if (!is_empty && !tty->flow.stopped)
- if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
- mxser_start_tx(info);
-
- return written;
-}
-
-static int mxser_put_char(struct tty_struct *tty, u8 ch)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&info->slock, flags);
- ret = kfifo_put(&info->port.xmit_fifo, ch);
- spin_unlock_irqrestore(&info->slock, flags);
-
- return ret;
-}
-
-
-static void mxser_flush_chars(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
- (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
- return;
-
- mxser_start_tx(info);
-}
-
-static unsigned int mxser_write_room(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- return kfifo_avail(&info->port.xmit_fifo);
-}
-
-static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- return kfifo_len(&info->port.xmit_fifo);
-}
-
-/*
- * ------------------------------------------------------------
- * friends of mxser_ioctl()
- * ------------------------------------------------------------
- */
-static int mxser_get_serial_info(struct tty_struct *tty,
- struct serial_struct *ss)
-{
- struct mxser_port *info = tty->driver_data;
- struct tty_port *port = &info->port;
- unsigned int closing_wait, close_delay;
-
- mutex_lock(&port->mutex);
-
- close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
- closing_wait = info->port.closing_wait;
- if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
- closing_wait = jiffies_to_msecs(closing_wait) / 10;
-
- ss->type = info->type;
- ss->line = tty->index;
- ss->port = info->ioaddr;
- ss->irq = info->board->irq;
- ss->flags = info->port.flags;
- ss->baud_base = MXSER_BAUD_BASE;
- ss->close_delay = close_delay;
- ss->closing_wait = closing_wait;
- ss->custom_divisor = MXSER_CUSTOM_DIVISOR;
- mutex_unlock(&port->mutex);
- return 0;
-}
-
-static int mxser_set_serial_info(struct tty_struct *tty,
- struct serial_struct *ss)
-{
- struct mxser_port *info = tty->driver_data;
- struct tty_port *port = &info->port;
- speed_t baud;
- unsigned long sl_flags;
- unsigned int old_speed, close_delay, closing_wait;
- int retval = 0;
-
- if (tty_io_error(tty))
- return -EIO;
-
- mutex_lock(&port->mutex);
-
- if (ss->irq != info->board->irq ||
- ss->port != info->ioaddr) {
- mutex_unlock(&port->mutex);
- return -EINVAL;
- }
-
- old_speed = port->flags & ASYNC_SPD_MASK;
-
- close_delay = msecs_to_jiffies(ss->close_delay * 10);
- closing_wait = ss->closing_wait;
- if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
- closing_wait = msecs_to_jiffies(closing_wait * 10);
-
- if (!capable(CAP_SYS_ADMIN)) {
- if ((ss->baud_base != MXSER_BAUD_BASE) ||
- (close_delay != port->close_delay) ||
- (closing_wait != port->closing_wait) ||
- ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
- mutex_unlock(&port->mutex);
- return -EPERM;
- }
- port->flags = (port->flags & ~ASYNC_USR_MASK) |
- (ss->flags & ASYNC_USR_MASK);
- } else {
- /*
- * OK, past this point, all the error checking has been done.
- * At this point, we start making changes.....
- */
- port->flags = ((port->flags & ~ASYNC_FLAGS) |
- (ss->flags & ASYNC_FLAGS));
- port->close_delay = close_delay;
- port->closing_wait = closing_wait;
- if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
- (ss->baud_base != MXSER_BAUD_BASE ||
- ss->custom_divisor !=
- MXSER_CUSTOM_DIVISOR)) {
- if (ss->custom_divisor == 0) {
- mutex_unlock(&port->mutex);
- return -EINVAL;
- }
- baud = ss->baud_base / ss->custom_divisor;
- tty_encode_baud_rate(tty, baud, baud);
- }
-
- info->type = ss->type;
-
- mxser_process_txrx_fifo(info);
- }
-
- if (tty_port_initialized(port)) {
- if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
- spin_lock_irqsave(&info->slock, sl_flags);
- mxser_change_speed(tty, NULL);
- spin_unlock_irqrestore(&info->slock, sl_flags);
- }
- } else {
- retval = mxser_activate(port, tty);
- if (retval == 0)
- tty_port_set_initialized(port, true);
- }
- mutex_unlock(&port->mutex);
- return retval;
-}
-
-/*
- * mxser_get_lsr_info - get line status register info
- *
- * Purpose: Let user call ioctl() to get info when the UART physically
- * is emptied. On bus types like RS485, the transmitter must
- * release the bus after transmitting. This must be done when
- * the transmit shift register is empty, not be done when the
- * transmit holding register is empty. This functionality
- * allows an RS485 driver to be written in user space.
- */
-static int mxser_get_lsr_info(struct mxser_port *info,
- unsigned int __user *value)
-{
- unsigned char status;
- unsigned int result;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- status = inb(info->ioaddr + UART_LSR);
- spin_unlock_irqrestore(&info->slock, flags);
- result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
- return put_user(result, value);
-}
-
-static int mxser_tiocmget(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned char control;
- unsigned long flags;
- u8 msr;
-
- if (tty_io_error(tty))
- return -EIO;
-
- spin_lock_irqsave(&info->slock, flags);
- control = info->MCR;
- msr = mxser_check_modem_status(tty, info);
- spin_unlock_irqrestore(&info->slock, flags);
-
- return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
- ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
- ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
- ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
- ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
- ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
-}
-
-static int mxser_tiocmset(struct tty_struct *tty,
- unsigned int set, unsigned int clear)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
-
- if (tty_io_error(tty))
- return -EIO;
-
- spin_lock_irqsave(&info->slock, flags);
-
- if (set & TIOCM_RTS)
- info->MCR |= UART_MCR_RTS;
- if (set & TIOCM_DTR)
- info->MCR |= UART_MCR_DTR;
-
- if (clear & TIOCM_RTS)
- info->MCR &= ~UART_MCR_RTS;
- if (clear & TIOCM_DTR)
- info->MCR &= ~UART_MCR_DTR;
-
- outb(info->MCR, info->ioaddr + UART_MCR);
- spin_unlock_irqrestore(&info->slock, flags);
- return 0;
-}
-
-static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
- struct async_icount *cprev)
-{
- struct async_icount cnow;
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&info->slock, flags);
- cnow = info->icount; /* atomic copy */
- spin_unlock_irqrestore(&info->slock, flags);
-
- ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
- ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
- ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
- ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
-
- *cprev = cnow;
-
- return ret;
-}
-
-/* We should likely switch to TIOCGRS485/TIOCSRS485. */
-static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
- int __user *u_opmode)
-{
- int opmode, p = index % 4;
- int shiftbit = p * 2;
- u8 val;
-
- if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
- return -EFAULT;
-
- if (set) {
- if (get_user(opmode, u_opmode))
- return -EFAULT;
-
- if (opmode & ~OP_MODE_MASK)
- return -EINVAL;
-
- spin_lock_irq(&port->slock);
- val = inb(port->opmode_ioaddr);
- val &= ~(OP_MODE_MASK << shiftbit);
- val |= (opmode << shiftbit);
- outb(val, port->opmode_ioaddr);
- spin_unlock_irq(&port->slock);
-
- return 0;
- }
-
- spin_lock_irq(&port->slock);
- opmode = inb(port->opmode_ioaddr) >> shiftbit;
- spin_unlock_irq(&port->slock);
-
- return put_user(opmode & OP_MODE_MASK, u_opmode);
-}
-
-static int mxser_ioctl(struct tty_struct *tty,
- unsigned int cmd, unsigned long arg)
-{
- struct mxser_port *info = tty->driver_data;
- struct async_icount cnow;
- unsigned long flags;
- void __user *argp = (void __user *)arg;
-
- if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
- return mxser_ioctl_op_mode(info, tty->index,
- cmd == MOXA_SET_OP_MODE, argp);
-
- if (cmd != TIOCMIWAIT && tty_io_error(tty))
- return -EIO;
-
- switch (cmd) {
- case TIOCSERGETLSR: /* Get line status register */
- return mxser_get_lsr_info(info, argp);
- /*
- * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
- * - mask passed in arg for lines of interest
- * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
- * Caller should use TIOCGICOUNT to see which one it was
- */
- case TIOCMIWAIT:
- spin_lock_irqsave(&info->slock, flags);
- cnow = info->icount; /* note the counters on entry */
- spin_unlock_irqrestore(&info->slock, flags);
-
- return wait_event_interruptible(info->port.delta_msr_wait,
- mxser_cflags_changed(info, arg, &cnow));
- default:
- return -ENOIOCTLCMD;
- }
- return 0;
-}
-
- /*
- * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
- * Return: write counters to the user passed counter struct
- * NB: both 1->0 and 0->1 transitions are counted except for
- * RI where only 0->1 is counted.
- */
-
-static int mxser_get_icount(struct tty_struct *tty,
- struct serial_icounter_struct *icount)
-
-{
- struct mxser_port *info = tty->driver_data;
- struct async_icount cnow;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- cnow = info->icount;
- spin_unlock_irqrestore(&info->slock, flags);
-
- icount->frame = cnow.frame;
- icount->brk = cnow.brk;
- icount->overrun = cnow.overrun;
- icount->buf_overrun = cnow.buf_overrun;
- icount->parity = cnow.parity;
- icount->rx = cnow.rx;
- icount->tx = cnow.tx;
- icount->cts = cnow.cts;
- icount->dsr = cnow.dsr;
- icount->rng = cnow.rng;
- icount->dcd = cnow.dcd;
- return 0;
-}
-
-/*
- * This routine is called by the upper-layer tty layer to signal that
- * incoming characters should be throttled.
- */
-static void mxser_throttle(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- if (I_IXOFF(tty)) {
- if (info->board->must_hwid) {
- info->IER &= ~MOXA_MUST_RECV_ISR;
- outb(info->IER, info->ioaddr + UART_IER);
- } else {
- info->x_char = STOP_CHAR(tty);
- outb(0, info->ioaddr + UART_IER);
- info->IER |= UART_IER_THRI;
- outb(info->IER, info->ioaddr + UART_IER);
- }
- }
-
- if (C_CRTSCTS(tty)) {
- info->MCR &= ~UART_MCR_RTS;
- outb(info->MCR, info->ioaddr + UART_MCR);
- }
-}
-
-static void mxser_unthrottle(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- /* startrx */
- if (I_IXOFF(tty)) {
- if (info->x_char)
- info->x_char = 0;
- else {
- if (info->board->must_hwid) {
- info->IER |= MOXA_MUST_RECV_ISR;
- outb(info->IER, info->ioaddr + UART_IER);
- } else {
- info->x_char = START_CHAR(tty);
- outb(0, info->ioaddr + UART_IER);
- info->IER |= UART_IER_THRI;
- outb(info->IER, info->ioaddr + UART_IER);
- }
- }
- }
-
- if (C_CRTSCTS(tty)) {
- info->MCR |= UART_MCR_RTS;
- outb(info->MCR, info->ioaddr + UART_MCR);
- }
-}
-
-/*
- * mxser_stop() and mxser_start()
- *
- * This routines are called before setting or resetting tty->flow.stopped.
- * They enable or disable transmitter interrupts, as necessary.
- */
-static void mxser_stop(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- if (info->IER & UART_IER_THRI)
- __mxser_stop_tx(info);
- spin_unlock_irqrestore(&info->slock, flags);
-}
-
-static void mxser_start(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- if (!kfifo_is_empty(&info->port.xmit_fifo))
- __mxser_start_tx(info);
- spin_unlock_irqrestore(&info->slock, flags);
-}
-
-static void mxser_set_termios(struct tty_struct *tty,
- const struct ktermios *old_termios)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
-
- spin_lock_irqsave(&info->slock, flags);
- mxser_change_speed(tty, old_termios);
- spin_unlock_irqrestore(&info->slock, flags);
-
- if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
- tty->hw_stopped = false;
- mxser_start(tty);
- }
-
- /* Handle sw stopped */
- if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
- tty->flow.stopped = 0;
-
- if (info->board->must_hwid) {
- spin_lock_irqsave(&info->slock, flags);
- mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
- spin_unlock_irqrestore(&info->slock, flags);
- }
-
- mxser_start(tty);
- }
-}
-
-static bool mxser_tx_empty(struct mxser_port *info)
-{
- unsigned long flags;
- u8 lsr;
-
- spin_lock_irqsave(&info->slock, flags);
- lsr = inb(info->ioaddr + UART_LSR);
- spin_unlock_irqrestore(&info->slock, flags);
-
- return !(lsr & UART_LSR_TEMT);
-}
-
-/*
- * mxser_wait_until_sent() --- wait until the transmitter is empty
- */
-static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long expire, char_time;
-
- if (info->type == PORT_UNKNOWN)
- return;
-
- if (info->xmit_fifo_size == 0)
- return; /* Just in case.... */
-
- /*
- * Set the check interval to be 1/5 of the estimated time to
- * send a single character, and make it at least 1. The check
- * interval should also be less than the timeout.
- *
- * Note: we have to use pretty tight timings here to satisfy
- * the NIST-PCTS.
- */
- char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
- char_time = char_time / 5;
- if (char_time == 0)
- char_time = 1;
- if (timeout && timeout < char_time)
- char_time = timeout;
-
- char_time = jiffies_to_msecs(char_time);
-
- /*
- * If the transmitter hasn't cleared in twice the approximate
- * amount of time to send the entire FIFO, it probably won't
- * ever clear. This assumes the UART isn't doing flow
- * control, which is currently the case. Hence, if it ever
- * takes longer than info->timeout, this is probably due to a
- * UART bug of some kind. So, we clamp the timeout parameter at
- * 2*info->timeout.
- */
- if (!timeout || timeout > 2 * info->timeout)
- timeout = 2 * info->timeout;
-
- expire = jiffies + timeout;
-
- while (mxser_tx_empty(info)) {
- msleep_interruptible(char_time);
- if (signal_pending(current))
- break;
- if (time_after(jiffies, expire))
- break;
- }
-}
-
-/*
- * This routine is called by tty_hangup() when a hangup is signaled.
- */
-static void mxser_hangup(struct tty_struct *tty)
-{
- struct mxser_port *info = tty->driver_data;
-
- mxser_flush_buffer(tty);
- tty_port_hangup(&info->port);
-}
-
-/*
- * mxser_rs_break() --- routine which turns the break handling on or off
- */
-static int mxser_rs_break(struct tty_struct *tty, int break_state)
-{
- struct mxser_port *info = tty->driver_data;
- unsigned long flags;
- u8 lcr;
-
- spin_lock_irqsave(&info->slock, flags);
- lcr = inb(info->ioaddr + UART_LCR);
- if (break_state == -1)
- lcr |= UART_LCR_SBC;
- else
- lcr &= ~UART_LCR_SBC;
- outb(lcr, info->ioaddr + UART_LCR);
- spin_unlock_irqrestore(&info->slock, flags);
-
- return 0;
-}
-
-static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
-{
- enum mxser_must_hwid hwid = port->board->must_hwid;
- u8 gdl;
-
- if (hwid == MOXA_OTHER_UART)
- return false;
- if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
- return false;
-
- gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
- if (hwid == MOXA_MUST_MU150_HWID)
- gdl &= MOXA_MUST_GDL_MASK;
-
- while (gdl--) {
- u8 ch = inb(port->ioaddr + UART_RX);
- if (!tty_insert_flip_char(&port->port, ch, 0))
- port->icount.buf_overrun++;
- }
-
- return true;
-}
-
-static u8 mxser_receive_chars_old(struct tty_struct *tty,
- struct mxser_port *port, u8 status)
-{
- enum mxser_must_hwid hwid = port->board->must_hwid;
- int ignored = 0;
- int max = 256;
- u8 ch;
-
- do {
- if (max-- < 0)
- break;
-
- ch = inb(port->ioaddr + UART_RX);
- if (hwid && (status & UART_LSR_OE))
- outb(port->FCR | UART_FCR_CLEAR_RCVR,
- port->ioaddr + UART_FCR);
- status &= port->read_status_mask;
- if (status & port->ignore_status_mask) {
- if (++ignored > 100)
- break;
- } else {
- u8 flag = 0;
- if (status & UART_LSR_BRK_ERROR_BITS) {
- if (status & UART_LSR_BI) {
- flag = TTY_BREAK;
- port->icount.brk++;
-
- if (port->port.flags & ASYNC_SAK)
- do_SAK(tty);
- } else if (status & UART_LSR_PE) {
- flag = TTY_PARITY;
- port->icount.parity++;
- } else if (status & UART_LSR_FE) {
- flag = TTY_FRAME;
- port->icount.frame++;
- } else if (status & UART_LSR_OE) {
- flag = TTY_OVERRUN;
- port->icount.overrun++;
- }
- }
- if (!tty_insert_flip_char(&port->port, ch, flag)) {
- port->icount.buf_overrun++;
- break;
- }
- }
-
- if (hwid)
- break;
-
- status = inb(port->ioaddr + UART_LSR);
- } while (status & UART_LSR_DR);
-
- return status;
-}
-
-static u8 mxser_receive_chars(struct tty_struct *tty,
- struct mxser_port *port, u8 status)
-{
- if (!mxser_receive_chars_new(port, status))
- status = mxser_receive_chars_old(tty, port, status);
-
- tty_flip_buffer_push(&port->port);
-
- return status;
-}
-
-static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
-{
- int count;
-
- if (port->x_char) {
- outb(port->x_char, port->ioaddr + UART_TX);
- port->x_char = 0;
- port->icount.tx++;
- return;
- }
-
- if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
- (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
- __mxser_stop_tx(port);
- return;
- }
-
- count = port->xmit_fifo_size;
- do {
- u8 c;
-
- if (!kfifo_get(&port->port.xmit_fifo, &c))
- break;
-
- outb(c, port->ioaddr + UART_TX);
- port->icount.tx++;
- } while (--count > 0);
-
- if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
- tty_wakeup(tty);
-
- if (kfifo_is_empty(&port->port.xmit_fifo))
- __mxser_stop_tx(port);
-}
-
-static bool mxser_port_isr(struct mxser_port *port)
-{
- struct tty_struct *tty;
- u8 iir, status;
- bool error = false;
-
- iir = inb(port->ioaddr + UART_IIR);
- if (iir & UART_IIR_NO_INT)
- return true;
-
- iir &= MOXA_MUST_IIR_MASK;
- tty = tty_port_tty_get(&port->port);
- if (!tty) {
- status = inb(port->ioaddr + UART_LSR);
- outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
- port->ioaddr + UART_FCR);
- inb(port->ioaddr + UART_MSR);
-
- error = true;
- goto put_tty;
- }
-
- status = inb(port->ioaddr + UART_LSR);
-
- if (port->board->must_hwid) {
- if (iir == MOXA_MUST_IIR_GDA ||
- iir == MOXA_MUST_IIR_RDA ||
- iir == MOXA_MUST_IIR_RTO ||
- iir == MOXA_MUST_IIR_LSR)
- status = mxser_receive_chars(tty, port, status);
- } else {
- status &= port->read_status_mask;
- if (status & UART_LSR_DR)
- status = mxser_receive_chars(tty, port, status);
- }
-
- mxser_check_modem_status(tty, port);
-
- if (port->board->must_hwid) {
- if (iir == 0x02 && (status & UART_LSR_THRE))
- mxser_transmit_chars(tty, port);
- } else {
- if (status & UART_LSR_THRE)
- mxser_transmit_chars(tty, port);
- }
-
-put_tty:
- tty_kref_put(tty);
-
- return error;
-}
-
-/*
- * This is the serial driver's generic interrupt routine
- */
-static irqreturn_t mxser_interrupt(int irq, void *dev_id)
-{
- struct mxser_board *brd = dev_id;
- struct mxser_port *port;
- unsigned int int_cnt, pass_counter = 0;
- unsigned int i, max = brd->nports;
- int handled = IRQ_NONE;
- u8 irqbits, bits, mask = BIT(max) - 1;
-
- while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
- irqbits = inb(brd->vector) & mask;
- if (irqbits == mask)
- break;
-
- handled = IRQ_HANDLED;
- for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
- if (irqbits == mask)
- break;
- if (bits & irqbits)
- continue;
- port = &brd->ports[i];
-
- int_cnt = 0;
- spin_lock(&port->slock);
- do {
- if (mxser_port_isr(port))
- break;
- } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
- spin_unlock(&port->slock);
- }
- }
-
- return handled;
-}
-
-static const struct tty_operations mxser_ops = {
- .open = mxser_open,
- .close = mxser_close,
- .write = mxser_write,
- .put_char = mxser_put_char,
- .flush_chars = mxser_flush_chars,
- .write_room = mxser_write_room,
- .chars_in_buffer = mxser_chars_in_buffer,
- .flush_buffer = mxser_flush_buffer,
- .ioctl = mxser_ioctl,
- .throttle = mxser_throttle,
- .unthrottle = mxser_unthrottle,
- .set_termios = mxser_set_termios,
- .stop = mxser_stop,
- .start = mxser_start,
- .hangup = mxser_hangup,
- .break_ctl = mxser_rs_break,
- .wait_until_sent = mxser_wait_until_sent,
- .tiocmget = mxser_tiocmget,
- .tiocmset = mxser_tiocmset,
- .set_serial = mxser_set_serial_info,
- .get_serial = mxser_get_serial_info,
- .get_icount = mxser_get_icount,
-};
-
-static const struct tty_port_operations mxser_port_ops = {
- .carrier_raised = mxser_carrier_raised,
- .dtr_rts = mxser_dtr_rts,
- .activate = mxser_activate,
- .shutdown = mxser_shutdown_port,
-};
-
-/*
- * The MOXA Smartio/Industio serial driver boot-time initialization code!
- */
-
-static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
-{
- struct mxser_port *info;
- unsigned int i;
- bool is_mu860;
-
- brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
- is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
-
- for (i = 0; i < UART_INFO_NUM; i++) {
- if (Gpci_uart_info[i].type == brd->must_hwid) {
- brd->max_baud = Gpci_uart_info[i].max_baud;
-
- /* exception....CP-102 */
- if (high_baud)
- brd->max_baud = 921600;
- break;
- }
- }
-
- if (is_mu860) {
- /* set to RS232 mode by default */
- outb(0, brd->vector + 4);
- outb(0, brd->vector + 0x0c);
- }
-
- for (i = 0; i < brd->nports; i++) {
- info = &brd->ports[i];
- if (is_mu860) {
- if (i < 4)
- info->opmode_ioaddr = brd->vector + 4;
- else
- info->opmode_ioaddr = brd->vector + 0x0c;
- }
- tty_port_init(&info->port);
- info->port.ops = &mxser_port_ops;
- info->board = brd;
-
- /* Enhance mode enabled here */
- if (brd->must_hwid != MOXA_OTHER_UART)
- mxser_must_set_enhance_mode(info->ioaddr, true);
-
- info->type = PORT_16550A;
-
- mxser_process_txrx_fifo(info);
-
- spin_lock_init(&info->slock);
-
- /* before set INT ISR, disable all int */
- outb(inb(info->ioaddr + UART_IER) & 0xf0,
- info->ioaddr + UART_IER);
- }
-}
-
-static int mxser_probe(struct pci_dev *pdev,
- const struct pci_device_id *ent)
-{
- struct mxser_board *brd;
- unsigned int i, base;
- unsigned long ioaddress;
- unsigned short nports = MXSER_NPORTS(ent->driver_data);
- struct device *tty_dev;
- int retval = -EINVAL;
-
- i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
- if (i >= MXSER_BOARDS) {
- dev_err(&pdev->dev, "too many boards found (maximum %d), board "
- "not configured\n", MXSER_BOARDS);
- goto err;
- }
-
- brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
- GFP_KERNEL);
- if (!brd)
- goto err;
-
- brd->idx = i;
- __set_bit(brd->idx, mxser_boards);
- base = i * MXSER_PORTS_PER_BOARD;
-
- retval = pcim_enable_device(pdev);
- if (retval) {
- dev_err(&pdev->dev, "PCI enable failed\n");
- goto err_zero;
- }
-
- /* io address */
- ioaddress = pci_resource_start(pdev, 2);
- retval = pci_request_region(pdev, 2, "mxser(IO)");
- if (retval)
- goto err_zero;
-
- brd->nports = nports;
- for (i = 0; i < nports; i++)
- brd->ports[i].ioaddr = ioaddress + 8 * i;
-
- /* vector */
- ioaddress = pci_resource_start(pdev, 3);
- retval = pci_request_region(pdev, 3, "mxser(vector)");
- if (retval)
- goto err_zero;
- brd->vector = ioaddress;
-
- /* irq */
- brd->irq = pdev->irq;
-
- mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
-
- retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
- IRQF_SHARED, "mxser", brd);
- if (retval) {
- dev_err(&pdev->dev, "request irq failed");
- goto err_relbrd;
- }
-
- for (i = 0; i < nports; i++) {
- tty_dev = tty_port_register_device(&brd->ports[i].port,
- mxvar_sdriver, base + i, &pdev->dev);
- if (IS_ERR(tty_dev)) {
- retval = PTR_ERR(tty_dev);
- for (; i > 0; i--)
- tty_unregister_device(mxvar_sdriver,
- base + i - 1);
- goto err_relbrd;
- }
- }
-
- pci_set_drvdata(pdev, brd);
-
- return 0;
-err_relbrd:
- for (i = 0; i < nports; i++)
- tty_port_destroy(&brd->ports[i].port);
-err_zero:
- __clear_bit(brd->idx, mxser_boards);
-err:
- return retval;
-}
-
-static void mxser_remove(struct pci_dev *pdev)
-{
- struct mxser_board *brd = pci_get_drvdata(pdev);
- unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
-
- for (i = 0; i < brd->nports; i++) {
- tty_unregister_device(mxvar_sdriver, base + i);
- tty_port_destroy(&brd->ports[i].port);
- }
-
- __clear_bit(brd->idx, mxser_boards);
-}
-
-static struct pci_driver mxser_driver = {
- .name = "mxser",
- .id_table = mxser_pcibrds,
- .probe = mxser_probe,
- .remove = mxser_remove
-};
-
-static int __init mxser_module_init(void)
-{
- int retval;
-
- mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
- TTY_DRIVER_DYNAMIC_DEV);
- if (IS_ERR(mxvar_sdriver))
- return PTR_ERR(mxvar_sdriver);
-
- /* Initialize the tty_driver structure */
- mxvar_sdriver->name = "ttyMI";
- mxvar_sdriver->major = ttymajor;
- mxvar_sdriver->minor_start = 0;
- mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
- mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
- mxvar_sdriver->init_termios = tty_std_termios;
- mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
- tty_set_operations(mxvar_sdriver, &mxser_ops);
-
- retval = tty_register_driver(mxvar_sdriver);
- if (retval) {
- printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
- "tty driver !\n");
- goto err_put;
- }
-
- retval = pci_register_driver(&mxser_driver);
- if (retval) {
- printk(KERN_ERR "mxser: can't register pci driver\n");
- goto err_unr;
- }
-
- return 0;
-err_unr:
- tty_unregister_driver(mxvar_sdriver);
-err_put:
- tty_driver_kref_put(mxvar_sdriver);
- return retval;
-}
-
-static void __exit mxser_module_exit(void)
-{
- pci_unregister_driver(&mxser_driver);
- tty_unregister_driver(mxvar_sdriver);
- tty_driver_kref_put(mxvar_sdriver);
-}
-
-module_init(mxser_module_init);
-module_exit(mxser_module_exit);
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
new file mode 100644
index 000000000000..fe899ff090c4
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * 8250_mxupci.c - Moxa UPCI multiport serial device driver
+ *
+ * Copyright (C) 2025 Moxa Inc. (support@moxa.com)
+ * Author: Crescent Hsieh <crescentcy.hsieh@moxa.com>
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/8250_pci.h>
+
+#include "8250.h"
+#include "8250_pcilib.h"
+
+#define PCI_DEVICE_ID_MOXA_RC7000 0x0001
+#define PCI_DEVICE_ID_MOXA_CP102 0x1020
+#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
+#define PCI_DEVICE_ID_MOXA_CP102U 0x1022
+#define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
+#define PCI_DEVICE_ID_MOXA_C104 0x1040
+#define PCI_DEVICE_ID_MOXA_CP104U 0x1041
+#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
+#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
+#define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
+#define PCI_DEVICE_ID_MOXA_CB108 0x1080
+#define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
+#define PCI_DEVICE_ID_MOXA_CT114 0x1140
+#define PCI_DEVICE_ID_MOXA_CP114 0x1141
+#define PCI_DEVICE_ID_MOXA_CB114 0x1142
+#define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
+#define PCI_DEVICE_ID_MOXA_CP118U 0x1180
+#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
+#define PCI_DEVICE_ID_MOXA_CP132 0x1320
+#define PCI_DEVICE_ID_MOXA_CP132U 0x1321
+#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
+#define PCI_DEVICE_ID_MOXA_CB134I 0x1341
+#define PCI_DEVICE_ID_MOXA_CP138U 0x1380
+#define PCI_DEVICE_ID_MOXA_C168 0x1680
+#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
+#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
+
+#define MOXA_UART_BASE_BAUD 921600
+#define MOXA_UART_OFFSET 8
+
+struct mxupci8250 {
+ struct pci_dev *pdev;
+ unsigned int num_ports;
+ int line[];
+};
+
+static unsigned short mxupci8250_get_nports(unsigned short device)
+{
+ switch (device) {
+ case PCI_DEVICE_ID_MOXA_RC7000:
+ return 8;
+ }
+
+ return FIELD_GET(0x00F0, device);
+}
+
+static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct uart_8250_port up;
+ struct mxupci8250 *priv;
+ unsigned int i, num_ports;
+ int ret;
+
+ ret = pcim_enable_device(pdev);
+ pci_save_state(pdev);
+
+ if (ret)
+ return ret;
+
+ num_ports = mxupci8250_get_nports(pdev->device);
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, line, num_ports), GFP_KERNEL);
+
+ if (!priv)
+ return -ENOMEM;
+
+ priv->num_ports = num_ports;
+ priv->pdev = pdev;
+
+ memset(&up, 0, sizeof(up));
+
+ up.port.dev = &pdev->dev;
+ up.port.irq = pdev->irq;
+ up.port.uartclk = MOXA_UART_BASE_BAUD * 16;
+ up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+
+ for (i = 0; i < num_ports; i++) {
+ if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
+ break;
+
+ dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
+ up.port.iobase, up.port.irq, up.port.iotype);
+
+ priv->line[i] = serial8250_register_8250_port(&up);
+
+ if (priv->line[i] < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
+ up.port.iobase, up.port.irq,
+ up.port.iotype, priv->line[i]);
+ break;
+ }
+ }
+ pci_set_drvdata(pdev, priv);
+
+ return 0;
+}
+
+static void mxupci8250_remove(struct pci_dev *pdev)
+{
+ struct mxupci8250 *priv = pci_get_drvdata(pdev);
+ unsigned int i;
+
+ for (i = 0; i < priv->num_ports; i++)
+ serial8250_unregister_port(priv->line[i]);
+}
+
+static const struct pci_device_id mxupci8250_pci_ids[] = {
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UF), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_POS104UL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CB108), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112UL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CB114), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114UL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CB134I), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL), },
+ { }
+};
+
+static struct pci_driver mxupci8250_pci_driver = {
+ .name = "8250_mxupci",
+ .id_table = mxupci8250_pci_ids,
+ .probe = mxupci8250_probe,
+ .remove = mxupci8250_remove,
+};
+
+module_pci_driver(mxupci8250_pci_driver);
+MODULE_AUTHOR("Moxa Inc.");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Moxa UPCI Multiport Serial Device Driver");
+MODULE_DEVICE_TABLE(pci, mxupci8250_pci_ids);
+MODULE_IMPORT_NS("SERIAL_8250_PCI");
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index 55d26d16df9b..e8b2878f8ab0 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -157,6 +157,17 @@ config SERIAL_8250_EXAR
422x PCIe serial cards that are not covered by the more generic
SERIAL_8250_PCI option.
+config SERIAL_8250_MOXA_UPCI
+ tristate "8250/16550 Moxa UPCI device support"
+ depends on SERIAL_8250 && PCI
+ select SERIAL_8250_PCILIB
+ default SERIAL_8250
+ help
+ Say Y here if you have a Moxa UPCI serial card.
+
+ To compile this driver as a module, choose M here: the
+ module will be called 8250_mxupci.
+
config SERIAL_8250_HP300
tristate
depends on SERIAL_8250 && HP300
diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile
index 1516de629b61..da9d35911bd5 100644
--- a/drivers/tty/serial/8250/Makefile
+++ b/drivers/tty/serial/8250/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
obj-$(CONFIG_SERIAL_8250_LPSS) += 8250_lpss.o
obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o
+obj-$(CONFIG_SERIAL_8250_MOXA_UPCI) += 8250_mxupci.o
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 01/31] tty: mxser: serial: 8250: replace mxser with 8250-based driver
2025-11-30 10:41 ` [PATCH v1 01/31] tty: mxser: serial: 8250: replace mxser with 8250-based driver Crescent Hsieh
@ 2025-11-30 17:07 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:07 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Remove the legacy mxser driver and replace it with 8250-based
> implementation (8250_mxupci) for Moxa UPCI serial devices.
>
> This simplifies maintenance and improves integration with the existing
> 8250 serial infrastructure.
One obvious question (that I found no clear answer to in the commit
message): Does it mean all functionality is kept the same? (I think I
know the answer and this has to be summarised in the commit message.)
And one potential issue with the change: Please, instead of removing
the old option, use transition Kconfig to make sure users will get the
driver compiled when moving from old kernel configurations to a new
one. However, see above. it might be more tricky to achieve a smooth
transition at the end.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 02/31] serial: 8250: add MU860 UART configuration
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
2025-11-30 10:41 ` [PATCH v1 01/31] tty: mxser: serial: 8250: replace mxser with 8250-based driver Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:10 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 03/31] serial: 8250_mxupci: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
` (28 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
The MU860 UART does not fully conform to PORT_16650V2 or any other
standard UART configuration. This patch introduces a new UART type,
PORT_MU860, to accurately reflect the hardware characteristics of
MU860-based devices.
The new configuration is applied to Moxa UPCI serial boards to ensure
correct initialization and operation.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 3 ++-
drivers/tty/serial/8250/8250_port.c | 8 ++++++++
include/uapi/linux/serial_core.h | 3 +++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index fe899ff090c4..d7a4b838ec1f 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -87,7 +87,8 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.dev = &pdev->dev;
up.port.irq = pdev->irq;
up.port.uartclk = MOXA_UART_BASE_BAUD * 16;
- up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+ up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ up.port.type = PORT_MU860;
for (i = 0; i < num_ports; i++) {
if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 649e74e9b52f..7d022315b3aa 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -319,6 +319,14 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 8, 16, 30},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
+ [PORT_MU860] = {
+ .name = "Moxa MU860 UART",
+ .fifo_size = 128,
+ .tx_loadsz = 128,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+ .rxtrig_bytes = {1, 4, 8, 14},
+ .flags = UART_CAP_FIFO,
+ },
};
/* Uart divisor latch read */
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 9c007a106330..49c2fcb2e24c 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -100,6 +100,9 @@
/* TXX9 type number */
#define PORT_TXX9 64
+/* Moxa MU860 UART */
+#define PORT_MU860 65
+
/*Digi jsm */
#define PORT_JSM 69
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 02/31] serial: 8250: add MU860 UART configuration
2025-11-30 10:41 ` [PATCH v1 02/31] serial: 8250: add MU860 UART configuration Crescent Hsieh
@ 2025-11-30 17:10 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:10 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> The MU860 UART does not fully conform to PORT_16650V2 or any other
What are the differences? This list should justify the need for the new type.
> standard UART configuration. This patch introduces a new UART type,
Imperative voice as suggested by Submitting Patch documentation.
> PORT_MU860, to accurately reflect the hardware characteristics of
> MU860-based devices.
>
> The new configuration is applied to Moxa UPCI serial boards to ensure
> correct initialization and operation.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 03/31] serial: 8250_mxupci: enable enhanced mode and custom FIFO trigger levels
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
2025-11-30 10:41 ` [PATCH v1 01/31] tty: mxser: serial: 8250: replace mxser with 8250-based driver Crescent Hsieh
2025-11-30 10:41 ` [PATCH v1 02/31] serial: 8250: add MU860 UART configuration Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:13 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 04/31] serial: 8250_mxupci: enable auto RTS/CTS flow control Crescent Hsieh
` (27 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add support for enabling enhanced mode and configuring custom FIFO trigger
levels on Moxa UPCI serial boards.
Enhanced mode is activated via EFR, which also provides access to three
configuration pages selected through EFR[7:6].
These pages allow fine-tuning of advanced UART feature such as Rx/Tx
interrupt trigger levels and flow control thresholds.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 65 +++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index d7a4b838ec1f..c4fa52de8962 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -43,6 +43,25 @@
#define MOXA_UART_BASE_BAUD 921600
#define MOXA_UART_OFFSET 8
+/* Enhanced Function Register (EFR) */
+/*
+ * EFR[7:6] - Enhanced Register Page Select:
+ * 00b (0x00) = Software flow control characters
+ * 01b (0x40) = FIFO trigger level
+ * 10b (0x80) = Clock, ID, reset
+ * 11b (0xC0) = Alias of Page 2 (same behavior as 10b)
+ */
+#define MOXA_UART_EFR_PAGE_0 0x00 /* Software flow control characters */
+#define MOXA_UART_EFR_PAGE_1 0x40 /* FIFO trigger level */
+#define MOXA_UART_EFR_PAGE_2 0x80 /* Clock, ID, reset */
+#define MOXA_UART_EFR_PAGE_MASK GENMASK(7, 6)
+
+/* Enhanced Registers Page 1 */
+#define MOXA_UART_RBRTL 0x04 /* Flow Control Low Trigger Level */
+#define MOXA_UART_RBRTH 0x05 /* Flow Control High Trigger Level */
+#define MOXA_UART_RBRTI 0x06 /* Rx Interrupt Trigger Level */
+#define MOXA_UART_THRTL 0x07 /* Tx Interrupt Trigger Level */
+
struct mxupci8250 {
struct pci_dev *pdev;
unsigned int num_ports;
@@ -59,6 +78,49 @@ static unsigned short mxupci8250_get_nports(unsigned short device)
return FIELD_GET(0x00F0, device);
}
+static int mxupci8250_startup(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ int ret;
+ u8 efr;
+
+ ret = serial8250_do_startup(port);
+
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+
+ efr = serial_in(up, UART_EFR);
+ efr |= UART_EFR_ECB;
+ serial_out(up, UART_EFR, efr);
+
+ efr &= ~MOXA_UART_EFR_PAGE_MASK;
+ efr |= MOXA_UART_EFR_PAGE_1;
+ serial_out(up, UART_EFR, efr);
+
+ serial_out(up, MOXA_UART_THRTL, 0);
+ serial_out(up, MOXA_UART_RBRTI, 96);
+ serial_out(up, MOXA_UART_RBRTL, 32);
+ serial_out(up, MOXA_UART_RBRTH, 96);
+
+ serial_out(up, UART_LCR, up->lcr);
+
+ return ret;
+}
+
+static void mxupci8250_shutdown(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ u8 efr;
+
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+
+ efr = serial_in(up, UART_EFR);
+ serial_out(up, UART_EFR, efr & ~UART_EFR_ECB);
+
+ serial_out(up, UART_LCR, up->lcr);
+
+ serial8250_do_shutdown(port);
+}
+
static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
@@ -90,6 +152,9 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
up.port.type = PORT_MU860;
+ up.port.startup = mxupci8250_startup;
+ up.port.shutdown = mxupci8250_shutdown;
+
for (i = 0; i < num_ports; i++) {
if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
break;
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 03/31] serial: 8250_mxupci: enable enhanced mode and custom FIFO trigger levels
2025-11-30 10:41 ` [PATCH v1 03/31] serial: 8250_mxupci: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
@ 2025-11-30 17:13 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:13 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add support for enabling enhanced mode and configuring custom FIFO trigger
> levels on Moxa UPCI serial boards.
>
> Enhanced mode is activated via EFR, which also provides access to three
> configuration pages selected through EFR[7:6].
> These pages allow fine-tuning of advanced UART feature such as Rx/Tx
features
> interrupt trigger levels and flow control thresholds.
...
> +static int mxupci8250_startup(struct uart_port *port)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + int ret;
> + u8 efr;
> +
> + ret = serial8250_do_startup(port);
This needs a very good comment on why it is okay to continue even in
error cases.
> + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
> +
> + efr = serial_in(up, UART_EFR);
> + efr |= UART_EFR_ECB;
> + serial_out(up, UART_EFR, efr);
> +
> + efr &= ~MOXA_UART_EFR_PAGE_MASK;
> + efr |= MOXA_UART_EFR_PAGE_1;
> + serial_out(up, UART_EFR, efr);
> +
> + serial_out(up, MOXA_UART_THRTL, 0);
> + serial_out(up, MOXA_UART_RBRTI, 96);
> + serial_out(up, MOXA_UART_RBRTL, 32);
> + serial_out(up, MOXA_UART_RBRTH, 96);
> +
> + serial_out(up, UART_LCR, up->lcr);
> +
> + return ret;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 04/31] serial: 8250_mxupci: enable auto RTS/CTS flow control
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (2 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 03/31] serial: 8250_mxupci: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:17 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 05/31] serial: 8250_mxupci: enable on-chip software " Crescent Hsieh
` (26 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Implement a custom set_termios() to configure RTS/CTS hardware flow
control. When CRTSCTS is enabled in termios, the UART_MCR[5] AFE (Auto
Flow Control Enable) bit is set to allow automatic RTS/CTS signaling.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index c4fa52de8962..54e50cd3f472 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -78,6 +78,26 @@ static unsigned short mxupci8250_get_nports(unsigned short device)
return FIELD_GET(0x00F0, device);
}
+static void mxupci8250_set_termios(struct uart_port *port, struct ktermios *new,
+ const struct ktermios *old)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int cflag = tty->termios.c_cflag;
+
+ serial8250_do_set_termios(port, new, old);
+
+ up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+
+ up->mcr &= ~UART_MCR_AFE;
+
+ if (cflag & CRTSCTS) {
+ up->mcr |= (UART_MCR_AFE | UART_MCR_RTS);
+ up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+ }
+ serial_out(up, UART_MCR, up->mcr);
+}
+
static int mxupci8250_startup(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -152,6 +172,7 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
up.port.type = PORT_MU860;
+ up.port.set_termios = mxupci8250_set_termios;
up.port.startup = mxupci8250_startup;
up.port.shutdown = mxupci8250_shutdown;
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 04/31] serial: 8250_mxupci: enable auto RTS/CTS flow control
2025-11-30 10:41 ` [PATCH v1 04/31] serial: 8250_mxupci: enable auto RTS/CTS flow control Crescent Hsieh
@ 2025-11-30 17:17 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:17 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Implement a custom set_termios() to configure RTS/CTS hardware flow
> control. When CRTSCTS is enabled in termios, the UART_MCR[5] AFE (Auto
> Flow Control Enable) bit is set to allow automatic RTS/CTS signaling.
...
> +static void mxupci8250_set_termios(struct uart_port *port, struct ktermios *new,
> + const struct ktermios *old)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + struct tty_struct *tty = port->state->port.tty;
> + unsigned int cflag = tty->termios.c_cflag;
> +
> + serial8250_do_set_termios(port, new, old);
> +
> + up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
> +
> + up->mcr &= ~UART_MCR_AFE;
> +
> + if (cflag & CRTSCTS) {
> + up->mcr |= (UART_MCR_AFE | UART_MCR_RTS);
> + up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
> + }
> + serial_out(up, UART_MCR, up->mcr);
> +}
Here I have a déjà vu feeling, i.e. some other drivers may also do the
same or very similar steps to enable it (8250_dw?). Can we create a
helper for all of them? And if this is the case, perhaps add it to
8250_pcilib.c?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 05/31] serial: 8250_mxupci: enable on-chip software flow control
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (3 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 04/31] serial: 8250_mxupci: enable auto RTS/CTS flow control Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 10:41 ` [PATCH v1 06/31] serial: 8250_mxupci: add custom handle_irq() Crescent Hsieh
` (25 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Extend set_termios() to support on-chip software flow control using the
Enhanced Feature Register (EFR). When IXON/IXOFF is enabled in termios,
EFR[3:0] is configured to enable in-band XON/XOFF flow control.
Corresponding XON1/XOFF1 characters are written via EFR page 0.
This patch also implements throttle() and unthrottle() to handle receive
pause and resume based on software flow control.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 75 ++++++++++++++++++++++++++-
1 file changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index 54e50cd3f472..99bd3e504549 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -45,17 +45,37 @@
/* Enhanced Function Register (EFR) */
/*
+ * EFR[1:0] - In-Band Receive Flow Control Mode (Compare XON/XOFF):
+ * 00b (0x00) = Disabled
+ * 01b (0x01) = Recognize XON2 & XOFF2 as XOFF character
+ * 10b (0x02) = Recognize XON1 & XOFF1 as XOFF character
+ * 11b (0x03) = Recognize XON1, XON2 & XOFF1, XOFF2 as XOFF character
+ * EFR[3:2] - In-Band Transmit Flow Control Mode (Insert XON/XOFF):
+ * 00b (0x00) = Disabled
+ * 01b (0x04) = Use XON2 & XOFF2 as XOFF character
+ * 10b (0x08) = Use XON1 & XOFF1 as XOFF character
+ * 11b (0x0C) = Use XON1, XON2 & XOFF1, XOFF2 as XOFF character
* EFR[7:6] - Enhanced Register Page Select:
* 00b (0x00) = Software flow control characters
* 01b (0x40) = FIFO trigger level
* 10b (0x80) = Clock, ID, reset
* 11b (0xC0) = Alias of Page 2 (same behavior as 10b)
*/
+#define MOXA_UART_EFR_RX_FLOW 0x02 /* Recognize XON1 & XOFF1 as XOFF character */
+#define MOXA_UART_EFR_TX_FLOW 0x08 /* Use XON1 & XOFF1 as XOFF character */
#define MOXA_UART_EFR_PAGE_0 0x00 /* Software flow control characters */
#define MOXA_UART_EFR_PAGE_1 0x40 /* FIFO trigger level */
#define MOXA_UART_EFR_PAGE_2 0x80 /* Clock, ID, reset */
+#define MOXA_UART_EFR_RX_FLOW_MASK GENMASK(1, 0)
+#define MOXA_UART_EFR_TX_FLOW_MASK GENMASK(3, 2)
#define MOXA_UART_EFR_PAGE_MASK GENMASK(7, 6)
+/* Enhanced Registers Page 0 */
+#define MOXA_UART_XON1 0x04
+#define MOXA_UART_XON2 0x05
+#define MOXA_UART_XOFF1 0x06
+#define MOXA_UART_XOFF2 0x07
+
/* Enhanced Registers Page 1 */
#define MOXA_UART_RBRTL 0x04 /* Flow Control Low Trigger Level */
#define MOXA_UART_RBRTH 0x05 /* Flow Control High Trigger Level */
@@ -84,10 +104,11 @@ static void mxupci8250_set_termios(struct uart_port *port, struct ktermios *new,
struct uart_8250_port *up = up_to_u8250p(port);
struct tty_struct *tty = port->state->port.tty;
unsigned int cflag = tty->termios.c_cflag;
+ u8 efr;
serial8250_do_set_termios(port, new, old);
- up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+ up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS | UPSTAT_AUTOXOFF);
up->mcr &= ~UART_MCR_AFE;
@@ -96,6 +117,31 @@ static void mxupci8250_set_termios(struct uart_port *port, struct ktermios *new,
up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
}
serial_out(up, UART_MCR, up->mcr);
+
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+
+ efr = serial_in(up, UART_EFR);
+ efr &= ~MOXA_UART_EFR_PAGE_MASK;
+ efr |= MOXA_UART_EFR_PAGE_0;
+ serial_out(up, UART_EFR, efr);
+
+ /* Set on-chip software flow control character */
+ serial_out(up, MOXA_UART_XON1, START_CHAR(tty));
+ serial_out(up, MOXA_UART_XON2, START_CHAR(tty));
+ serial_out(up, MOXA_UART_XOFF1, STOP_CHAR(tty));
+ serial_out(up, MOXA_UART_XOFF2, STOP_CHAR(tty));
+
+ efr &= ~(MOXA_UART_EFR_RX_FLOW_MASK | MOXA_UART_EFR_TX_FLOW_MASK);
+
+ if (I_IXON(tty))
+ efr |= MOXA_UART_EFR_RX_FLOW;
+
+ if (I_IXOFF(tty)) {
+ efr |= MOXA_UART_EFR_TX_FLOW;
+ up->port.status |= UPSTAT_AUTOXOFF;
+ }
+ serial_out(up, UART_EFR, efr);
+ serial_out(up, UART_LCR, up->lcr);
}
static int mxupci8250_startup(struct uart_port *port)
@@ -141,6 +187,31 @@ static void mxupci8250_shutdown(struct uart_port *port)
serial8250_do_shutdown(port);
}
+static void mxupci8250_throttle(struct uart_port *port)
+{
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ port->ops->stop_rx(port);
+
+ uart_port_unlock_irqrestore(port, flags);
+}
+
+static void mxupci8250_unthrottle(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ up->ier |= UART_IER_RLSI | UART_IER_RDI;
+ port->read_status_mask |= UART_LSR_DR;
+ serial_out(up, UART_IER, up->ier);
+
+ uart_port_unlock_irqrestore(port, flags);
+}
+
static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
@@ -175,6 +246,8 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.set_termios = mxupci8250_set_termios;
up.port.startup = mxupci8250_startup;
up.port.shutdown = mxupci8250_shutdown;
+ up.port.throttle = mxupci8250_throttle;
+ up.port.unthrottle = mxupci8250_unthrottle;
for (i = 0; i < num_ports; i++) {
if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 06/31] serial: 8250_mxupci: add custom handle_irq()
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (4 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 05/31] serial: 8250_mxupci: enable on-chip software " Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:20 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci Crescent Hsieh
` (24 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add a custom handle_irq() for 8250_mxupci based on serial8250_handle_irq(),
removing PM wakeup and DMA handling that are not needed.
This prepares for future adjustments to RX and TX behavior specific to
Moxa MU860 UART.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 36 +++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index 99bd3e504549..376c6d6135a3 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -212,6 +212,41 @@ static void mxupci8250_unthrottle(struct uart_port *port)
uart_port_unlock_irqrestore(port, flags);
}
+static int mxupci8250_handle_irq(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ bool skip_rx = false;
+ unsigned long flags;
+ u16 lsr;
+ u8 iir;
+
+ iir = serial_in(up, UART_IIR);
+
+ if (iir & UART_IIR_NO_INT)
+ return 0;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ lsr = serial_lsr_in(up);
+
+ if (!(lsr & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
+ (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
+ !(port->read_status_mask & UART_LSR_DR))
+ skip_rx = true;
+
+ if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
+ lsr = serial8250_rx_chars(up, lsr);
+
+ serial8250_modem_status(up);
+
+ if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
+ serial8250_tx_chars(up);
+
+ uart_unlock_and_check_sysrq_irqrestore(port, flags);
+
+ return 1;
+}
+
static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
@@ -248,6 +283,7 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.shutdown = mxupci8250_shutdown;
up.port.throttle = mxupci8250_throttle;
up.port.unthrottle = mxupci8250_unthrottle;
+ up.port.handle_irq = mxupci8250_handle_irq;
for (i = 0; i < num_ports; i++) {
if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 06/31] serial: 8250_mxupci: add custom handle_irq()
2025-11-30 10:41 ` [PATCH v1 06/31] serial: 8250_mxupci: add custom handle_irq() Crescent Hsieh
@ 2025-11-30 17:20 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:20 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add a custom handle_irq() for 8250_mxupci based on serial8250_handle_irq(),
> removing PM wakeup and DMA handling that are not needed.
>
> This prepares for future adjustments to RX and TX behavior specific to
> Moxa MU860 UART.
...
> +static int mxupci8250_handle_irq(struct uart_port *port)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + bool skip_rx = false;
> + unsigned long flags;
> + u16 lsr;
> + u8 iir;
> +
> + iir = serial_in(up, UART_IIR);
> +
Stray blank line addition.
> + if (iir & UART_IIR_NO_INT)
> + return 0;
> +
> + uart_port_lock_irqsave(port, &flags);
> +
> + lsr = serial_lsr_in(up);
> +
Ditto.
> + if (!(lsr & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
> + (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
> + !(port->read_status_mask & UART_LSR_DR))
> + skip_rx = true;
> +
> + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> + lsr = serial8250_rx_chars(up, lsr);
> +
> + serial8250_modem_status(up);
> +
> + if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
> + serial8250_tx_chars(up);
> +
> + uart_unlock_and_check_sysrq_irqrestore(port, flags);
> +
> + return 1;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (5 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 06/31] serial: 8250_mxupci: add custom handle_irq() Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 17:29 ` Andy Shevchenko
2025-11-30 10:41 ` [PATCH v1 08/31] serial: 8250_mxupci: add custom Tx " Crescent Hsieh
` (23 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Introduce a custom Rx routine using the GDL (Good Data Length) register to
read multiple bytes from the Rx FIFO on Moxa UPCI serial boards.
When no LSR error bits are present, the handler reads GDL bytes from
UART_RX and inserts them into the TTY flip buffer. If error bits are
detected, it falls back to the default serial8250_rx_chars() handler.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 37 ++++++++++++++++++++++++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index 376c6d6135a3..ab6042f157c6 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -8,6 +8,7 @@
#include <linux/module.h>
#include <linux/pci.h>
+#include <linux/tty_flip.h>
#include <linux/8250_pci.h>
#include "8250.h"
@@ -42,6 +43,7 @@
#define MOXA_UART_BASE_BAUD 921600
#define MOXA_UART_OFFSET 8
+#define MOXA_UART_FIFO_SIZE 128
/* Enhanced Function Register (EFR) */
/*
@@ -70,6 +72,8 @@
#define MOXA_UART_EFR_TX_FLOW_MASK GENMASK(3, 2)
#define MOXA_UART_EFR_PAGE_MASK GENMASK(7, 6)
+#define MOXA_UART_GDL 0x07 /* Good data length register (enhanced mode only) */
+
/* Enhanced Registers Page 0 */
#define MOXA_UART_XON1 0x04
#define MOXA_UART_XON2 0x05
@@ -212,6 +216,30 @@ static void mxupci8250_unthrottle(struct uart_port *port)
uart_port_unlock_irqrestore(port, flags);
}
+static void mxupci8250_rx_chars(struct uart_8250_port *up)
+{
+ struct uart_port *port = &up->port;
+ struct tty_port *tport = &port->state->port;
+ int recv_room, gdl, i;
+ u8 buf[MOXA_UART_FIFO_SIZE];
+
+ recv_room = tty_buffer_request_room(tport, port->fifosize);
+
+ if (recv_room) {
+ gdl = serial_in(up, MOXA_UART_GDL);
+
+ if (gdl > recv_room)
+ gdl = recv_room;
+
+ for (i = 0; i < gdl; ++i)
+ buf[i] = serial_in(up, UART_RX);
+
+ port->icount.rx += gdl;
+ tty_insert_flip_string(tport, buf, gdl);
+ tty_flip_buffer_push(tport);
+ }
+}
+
static int mxupci8250_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -234,9 +262,12 @@ static int mxupci8250_handle_irq(struct uart_port *port)
!(port->read_status_mask & UART_LSR_DR))
skip_rx = true;
- if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
- lsr = serial8250_rx_chars(up, lsr);
-
+ if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
+ if (lsr & UART_LSR_BRK_ERROR_BITS)
+ lsr = serial8250_rx_chars(up, lsr);
+ else
+ mxupci8250_rx_chars(up);
+ }
serial8250_modem_status(up);
if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci
2025-11-30 10:41 ` [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci Crescent Hsieh
@ 2025-11-30 17:29 ` Andy Shevchenko
2025-12-05 3:47 ` Crescent Hsieh
0 siblings, 1 reply; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 17:29 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Introduce a custom Rx routine using the GDL (Good Data Length) register to
> read multiple bytes from the Rx FIFO on Moxa UPCI serial boards.
>
> When no LSR error bits are present, the handler reads GDL bytes from
> UART_RX and inserts them into the TTY flip buffer. If error bits are
> detected, it falls back to the default serial8250_rx_chars() handler.
...
> +static void mxupci8250_rx_chars(struct uart_8250_port *up)
> +{
> + struct uart_port *port = &up->port;
> + struct tty_port *tport = &port->state->port;
> + int recv_room, gdl, i;
> + u8 buf[MOXA_UART_FIFO_SIZE];
> +
> + recv_room = tty_buffer_request_room(tport, port->fifosize);
> +
Stray blank line addition.
> + if (recv_room) {
Can't it be
if (!recv_room)
return;
?
> + gdl = serial_in(up, MOXA_UART_GDL);
> +
Stray blank line addition.
> + if (gdl > recv_room)
> + gdl = recv_room;
> +
> + for (i = 0; i < gdl; ++i)
> + buf[i] = serial_in(up, UART_RX);
> +
> + port->icount.rx += gdl;
> + tty_insert_flip_string(tport, buf, gdl);
> + tty_flip_buffer_push(tport);
> + }
> +}
...
> - if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> - lsr = serial8250_rx_chars(up, lsr);
> -
> + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
> + if (lsr & UART_LSR_BRK_ERROR_BITS)
> + lsr = serial8250_rx_chars(up, lsr);
> + else
> + mxupci8250_rx_chars(up);
> + }
Oh, can we reduce ping-pong a bit (the modification of the lines just
being added earlier in the same patch series)?
I think you can create a helper to wrap 8250_rx_chars() with split
version of the almost unreadable conditionals, this will also remove
the skip_rx variable
static ... _rx_chars()
{
/* split version of skip_rx monstrous if */
if ...
return ...;
if ...
return ...;
if ...
return ...;
return 8250_rx_chars(...);
}
Then in this patch only a couple of lines will be added to the end of
the function.
if (...)
return ...
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci
2025-11-30 17:29 ` Andy Shevchenko
@ 2025-12-05 3:47 ` Crescent Hsieh
2025-12-05 8:03 ` Andy Shevchenko
0 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-12-05 3:47 UTC (permalink / raw)
To: Andy Shevchenko
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 07:29:47PM +0200, Andy Shevchenko wrote:
> On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
> <crescentcy.hsieh@moxa.com> wrote:
> > - if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> > - lsr = serial8250_rx_chars(up, lsr);
> > -
> > + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
> > + if (lsr & UART_LSR_BRK_ERROR_BITS)
> > + lsr = serial8250_rx_chars(up, lsr);
> > + else
> > + mxupci8250_rx_chars(up);
> > + }
>
> Oh, can we reduce ping-pong a bit (the modification of the lines just
> being added earlier in the same patch series)?
>
> I think you can create a helper to wrap 8250_rx_chars() with split
> version of the almost unreadable conditionals, this will also remove
> the skip_rx variable
I want to confirm whether I understood your suggestion correctly:
Should I first introduce a small wrapper function for Rx processing,
move all the complicated Rx conditions into that wrapper so that
handle_irq() remains short and readable, and then, in a later patch,
introduce the actual custom Rx routine and update the wrapper to call
it?
---
Sincerely,
Crescent Hsieh
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci
2025-12-05 3:47 ` Crescent Hsieh
@ 2025-12-05 8:03 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-05 8:03 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Fri, Dec 5, 2025 at 5:47 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> On Sun, Nov 30, 2025 at 07:29:47PM +0200, Andy Shevchenko wrote:
> > On Sun, Nov 30, 2025 at 12:43 PM Crescent Hsieh
> > <crescentcy.hsieh@moxa.com> wrote:
> > > - if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> > > - lsr = serial8250_rx_chars(up, lsr);
> > > -
> > > + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
> > > + if (lsr & UART_LSR_BRK_ERROR_BITS)
> > > + lsr = serial8250_rx_chars(up, lsr);
> > > + else
> > > + mxupci8250_rx_chars(up);
> > > + }
> >
> > Oh, can we reduce ping-pong a bit (the modification of the lines just
> > being added earlier in the same patch series)?
> >
> > I think you can create a helper to wrap 8250_rx_chars() with split
> > version of the almost unreadable conditionals, this will also remove
> > the skip_rx variable
>
> I want to confirm whether I understood your suggestion correctly:
>
> Should I first introduce a small wrapper function for Rx processing,
> move all the complicated Rx conditions into that wrapper so that
> handle_irq() remains short and readable, and then, in a later patch,
> introduce the actual custom Rx routine and update the wrapper to call
> it?
Yes, something like
old_rx() {}
new_rx() {}
if (foo)
old_rx()
else
new_rx()
should be in the result.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 08/31] serial: 8250_mxupci: add custom Tx routine for 8250_mxupci
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (6 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 07/31] serial: 8250_mxupci: add GDL-based Rx routine for 8250_mxupci Crescent Hsieh
@ 2025-11-30 10:41 ` Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci Crescent Hsieh
` (22 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:41 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Implement a custom tx_chars() routine for Moxa MU860 UART to manage Tx
FIFO and xmit buffer handling.
The routine fetches up to fifosize bytes from the transmit FIFO and writes
them to UART_TX using serial_out(). Wakeup and stop_tx conditions are
handled based on FIFO state.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 33 ++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index ab6042f157c6..0eeaf0fa1538 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -240,6 +240,37 @@ static void mxupci8250_rx_chars(struct uart_8250_port *up)
}
}
+static void mxupci8250_tx_chars(struct uart_8250_port *up)
+{
+ struct uart_port *port = &up->port;
+ struct tty_port *tport = &port->state->port;
+ unsigned int count, i;
+ unsigned char c;
+
+ if (port->x_char) {
+ uart_xchar_out(port, UART_TX);
+ return;
+ }
+ if (uart_tx_stopped(port) || kfifo_is_empty(&tport->xmit_fifo)) {
+ port->ops->stop_tx(port);
+ return;
+ }
+ count = kfifo_len(&tport->xmit_fifo);
+ count = min(count, port->fifosize);
+
+ for (i = 0; i < count; ++i) {
+ if (!uart_fifo_get(port, &c))
+ break;
+
+ serial_out(up, UART_TX, c);
+ }
+ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (kfifo_is_empty(&tport->xmit_fifo) && !(up->capabilities & UART_CAP_RPM))
+ port->ops->stop_tx(port);
+}
+
static int mxupci8250_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -271,7 +302,7 @@ static int mxupci8250_handle_irq(struct uart_port *port)
serial8250_modem_status(up);
if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
- serial8250_tx_chars(up);
+ mxupci8250_tx_chars(up);
uart_unlock_and_check_sysrq_irqrestore(port, flags);
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (7 preceding siblings ...)
2025-11-30 10:41 ` [PATCH v1 08/31] serial: 8250_mxupci: add custom Tx " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 19:22 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 10/31] serial: 8250: add MUEx50 UART configuration Crescent Hsieh
` (21 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
To avoid polluting 8250_pci, as suggested by Andy Shevchenko, this patch
separates 8250_mxpcie into its own module.
- https://lore.kernel.org/all/ZmQovC6TbDpTb3c8@surfacebook.localdomain/
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 277 ++++++++++++++++++++++++++
drivers/tty/serial/8250/8250_pci.c | 205 -------------------
drivers/tty/serial/8250/Kconfig | 11 +
drivers/tty/serial/8250/Makefile | 1 +
4 files changed, 289 insertions(+), 205 deletions(-)
create mode 100644 drivers/tty/serial/8250/8250_mxpcie.c
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
new file mode 100644
index 000000000000..2e26307a9fee
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * 8250_mxpcie.c - Moxa PCIe multiport serial device driver
+ *
+ * Copyright (C) 2025 Moxa Inc. (support@moxa.com)
+ * Author: Crescent Hsieh <crescentcy.hsieh@moxa.com>
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/8250_pci.h>
+
+#include "8250.h"
+#include "8250_pcilib.h"
+
+#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
+#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
+#define PCI_DEVICE_ID_MOXA_CP102N 0x1027
+#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
+#define PCI_DEVICE_ID_MOXA_CP104N 0x1046
+#define PCI_DEVICE_ID_MOXA_CP112N 0x1121
+#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
+#define PCI_DEVICE_ID_MOXA_CP114N 0x1145
+#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
+#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
+#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
+#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
+#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
+#define PCI_DEVICE_ID_MOXA_CP132N 0x1323
+#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
+#define PCI_DEVICE_ID_MOXA_CP134N 0x1343
+#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
+#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
+
+/* UART */
+#define MOXA_PUART_BASE_BAUD 921600
+#define MOXA_PUART_OFFSET 0x200
+
+#define MOXA_GPIO_DIRECTION 0x09
+#define MOXA_GPIO_OUTPUT 0x0A
+
+#define MOXA_GPIO_PIN2 BIT(2)
+
+#define MOXA_UIR_OFFSET 0x04
+#define MOXA_UIR_RS232 0x00
+#define MOXA_UIR_RS422 0x01
+#define MOXA_UIR_RS485_4W 0x0B
+#define MOXA_UIR_RS485_2W 0x0F
+
+#define MOXA_EVEN_RS_MASK GENMASK(3, 0)
+#define MOXA_ODD_RS_MASK GENMASK(7, 4)
+
+struct mxpcie8250 {
+ struct pci_dev *pdev;
+ unsigned int supp_rs;
+ unsigned int num_ports;
+ int line[];
+};
+
+enum {
+ MOXA_SUPP_RS232 = BIT(0),
+ MOXA_SUPP_RS422 = BIT(1),
+ MOXA_SUPP_RS485 = BIT(2),
+};
+
+static bool mxpcie8250_is_mini_pcie(unsigned short device)
+{
+ if (device == PCI_DEVICE_ID_MOXA_CP102N ||
+ device == PCI_DEVICE_ID_MOXA_CP104N ||
+ device == PCI_DEVICE_ID_MOXA_CP112N ||
+ device == PCI_DEVICE_ID_MOXA_CP114N ||
+ device == PCI_DEVICE_ID_MOXA_CP132N ||
+ device == PCI_DEVICE_ID_MOXA_CP134N)
+ return true;
+
+ return false;
+}
+
+static unsigned int mxpcie8250_get_supp_rs(unsigned short device)
+{
+ switch (device & 0x0F00) {
+ case 0x0000:
+ case 0x0600:
+ return MOXA_SUPP_RS232;
+ case 0x0100:
+ return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
+ case 0x0300:
+ return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
+ }
+
+ return 0;
+}
+
+static unsigned short mxpcie8250_get_nports(unsigned short device)
+{
+ switch (device) {
+ case PCI_DEVICE_ID_MOXA_CP116E_A_A:
+ case PCI_DEVICE_ID_MOXA_CP116E_A_B:
+ return 8;
+ }
+
+ return FIELD_GET(0x00F0, device);
+}
+
+static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
+ unsigned int port_idx,
+ u8 mode)
+{
+ resource_size_t iobar_addr = pci_resource_start(priv->pdev, 2);
+ resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
+ u8 cval;
+
+ cval = inb(UIR_addr);
+
+ if (port_idx % 2) {
+ cval &= ~MOXA_ODD_RS_MASK;
+ cval |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
+ } else {
+ cval &= ~MOXA_EVEN_RS_MASK;
+ cval |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
+ }
+ outb(cval, UIR_addr);
+
+ return 0;
+}
+
+static int mxpcie8250_init(struct pci_dev *pdev)
+{
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ u8 cval;
+
+ /* Initial terminator */
+ if (pdev->device == PCI_DEVICE_ID_MOXA_CP114EL ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP118EL_A) {
+ outb(0xff, iobar_addr + MOXA_GPIO_DIRECTION);
+ outb(0x00, iobar_addr + MOXA_GPIO_OUTPUT);
+ }
+ /*
+ * Enable hardware buffer to prevent break signal output when system boots up.
+ * This hardware buffer is only supported on Mini PCIe series.
+ */
+ if (mxpcie8250_is_mini_pcie(pdev->device)) {
+ /* Set GPIO direction */
+ cval = inb(iobar_addr + MOXA_GPIO_DIRECTION);
+ cval |= MOXA_GPIO_PIN2;
+ outb(cval, iobar_addr + MOXA_GPIO_DIRECTION);
+ /* Enable low GPIO */
+ cval = inb(iobar_addr + MOXA_GPIO_OUTPUT);
+ cval &= ~MOXA_GPIO_PIN2;
+ outb(cval, iobar_addr + MOXA_GPIO_OUTPUT);
+ }
+
+ return 0;
+}
+
+static int mxpcie8250_setup(struct pci_dev *pdev,
+ struct mxpcie8250 *priv,
+ struct uart_8250_port *up,
+ int idx)
+{
+ unsigned int bar = FL_GET_BASE(FL_BASE1);
+ int offset = idx * MOXA_PUART_OFFSET;
+ u8 init_mode = MOXA_UIR_RS232;
+
+ if (!(priv->supp_rs & MOXA_SUPP_RS232))
+ init_mode = MOXA_UIR_RS422;
+
+ mxpcie8250_set_interface(priv, idx, init_mode);
+
+ if (idx == 3 &&
+ (pdev->device == PCI_DEVICE_ID_MOXA_CP104EL_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP114EL ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP134EL_A))
+ offset = 7 * MOXA_PUART_OFFSET;
+
+ return serial8250_pci_setup_port(pdev, up, bar, offset, 0);
+}
+
+static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct uart_8250_port up;
+ struct mxpcie8250 *priv;
+ unsigned int i, num_ports;
+ int ret;
+
+ ret = pcim_enable_device(pdev);
+ pci_save_state(pdev);
+
+ if (ret)
+ return ret;
+
+ num_ports = mxpcie8250_get_nports(pdev->device);
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, line, num_ports), GFP_KERNEL);
+
+ if (!priv)
+ return -ENOMEM;
+
+ priv->supp_rs = mxpcie8250_get_supp_rs(pdev->device);
+ priv->num_ports = num_ports;
+
+ mxpcie8250_init(pdev);
+ priv->pdev = pdev;
+
+ memset(&up, 0, sizeof(up));
+
+ up.port.dev = &pdev->dev;
+ up.port.irq = pdev->irq;
+ up.port.uartclk = MOXA_PUART_BASE_BAUD * 16;
+ up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+
+ for (i = 0; i < num_ports; i++) {
+ if (mxpcie8250_setup(pdev, priv, &up, i))
+ break;
+
+ dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
+ up.port.iobase, up.port.irq, up.port.iotype);
+
+ priv->line[i] = serial8250_register_8250_port(&up);
+
+ if (priv->line[i] < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
+ up.port.iobase, up.port.irq,
+ up.port.iotype, priv->line[i]);
+ break;
+ }
+ }
+ pci_set_drvdata(pdev, priv);
+
+ return 0;
+}
+
+static void mxpcie8250_remove(struct pci_dev *pdev)
+{
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ unsigned int i;
+
+ for (i = 0; i < priv->num_ports; i++)
+ serial8250_unregister_port(priv->line[i]);
+}
+
+static const struct pci_device_id mxpcie8250_pci_ids[] = {
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A) },
+ { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A) },
+ { }
+};
+
+static struct pci_driver mxpcie8250_pci_driver = {
+ .name = "8250_mxpcie",
+ .id_table = mxpcie8250_pci_ids,
+ .probe = mxpcie8250_probe,
+ .remove = mxpcie8250_remove,
+};
+
+module_pci_driver(mxpcie8250_pci_driver);
+MODULE_AUTHOR("Moxa Inc.");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Moxa PCIe Multiport Serial Device Driver");
+MODULE_DEVICE_TABLE(pci, mxpcie8250_pci_ids);
+MODULE_IMPORT_NS("SERIAL_8250_PCI");
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 3c3f7c926afb..7327a370318e 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -82,25 +82,6 @@
#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
-#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
-#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
-#define PCI_DEVICE_ID_MOXA_CP102N 0x1027
-#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
-#define PCI_DEVICE_ID_MOXA_CP104N 0x1046
-#define PCI_DEVICE_ID_MOXA_CP112N 0x1121
-#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
-#define PCI_DEVICE_ID_MOXA_CP114N 0x1145
-#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
-#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
-#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
-#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
-#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
-#define PCI_DEVICE_ID_MOXA_CP132N 0x1323
-#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
-#define PCI_DEVICE_ID_MOXA_CP134N 0x1343
-#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
-#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
-
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
@@ -2000,138 +1981,6 @@ pci_sunix_setup(struct serial_private *priv,
return setup_port(priv, port, bar, offset, 0);
}
-#define MOXA_PUART_GPIO_EN 0x09
-#define MOXA_PUART_GPIO_OUT 0x0A
-
-#define MOXA_GPIO_PIN2 BIT(2)
-
-#define MOXA_RS232 0x00
-#define MOXA_RS422 0x01
-#define MOXA_RS485_4W 0x0B
-#define MOXA_RS485_2W 0x0F
-#define MOXA_UIR_OFFSET 0x04
-#define MOXA_EVEN_RS_MASK GENMASK(3, 0)
-#define MOXA_ODD_RS_MASK GENMASK(7, 4)
-
-enum {
- MOXA_SUPP_RS232 = BIT(0),
- MOXA_SUPP_RS422 = BIT(1),
- MOXA_SUPP_RS485 = BIT(2),
-};
-
-static unsigned short moxa_get_nports(unsigned short device)
-{
- switch (device) {
- case PCI_DEVICE_ID_MOXA_CP116E_A_A:
- case PCI_DEVICE_ID_MOXA_CP116E_A_B:
- return 8;
- }
-
- return FIELD_GET(0x00F0, device);
-}
-
-static bool pci_moxa_is_mini_pcie(unsigned short device)
-{
- if (device == PCI_DEVICE_ID_MOXA_CP102N ||
- device == PCI_DEVICE_ID_MOXA_CP104N ||
- device == PCI_DEVICE_ID_MOXA_CP112N ||
- device == PCI_DEVICE_ID_MOXA_CP114N ||
- device == PCI_DEVICE_ID_MOXA_CP132N ||
- device == PCI_DEVICE_ID_MOXA_CP134N)
- return true;
-
- return false;
-}
-
-static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
-{
- switch (dev->device & 0x0F00) {
- case 0x0000:
- case 0x0600:
- return MOXA_SUPP_RS232;
- case 0x0100:
- return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
- case 0x0300:
- return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
- }
- return 0;
-}
-
-static int pci_moxa_set_interface(const struct pci_dev *dev,
- unsigned int port_idx,
- u8 mode)
-{
- resource_size_t iobar_addr = pci_resource_start(dev, 2);
- resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
- u8 val;
-
- val = inb(UIR_addr);
-
- if (port_idx % 2) {
- val &= ~MOXA_ODD_RS_MASK;
- val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
- } else {
- val &= ~MOXA_EVEN_RS_MASK;
- val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
- }
- outb(val, UIR_addr);
-
- return 0;
-}
-
-static int pci_moxa_init(struct pci_dev *dev)
-{
- unsigned short device = dev->device;
- resource_size_t iobar_addr = pci_resource_start(dev, 2);
- unsigned int i, num_ports = moxa_get_nports(device);
- u8 val, init_mode = MOXA_RS232;
-
- if (!IS_ENABLED(CONFIG_HAS_IOPORT))
- return serial_8250_warn_need_ioport(dev);
-
- if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
- init_mode = MOXA_RS422;
- }
- for (i = 0; i < num_ports; ++i)
- pci_moxa_set_interface(dev, i, init_mode);
-
- /*
- * Enable hardware buffer to prevent break signal output when system boots up.
- * This hardware buffer is only supported on Mini PCIe series.
- */
- if (pci_moxa_is_mini_pcie(device)) {
- /* Set GPIO direction */
- val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
- val |= MOXA_GPIO_PIN2;
- outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
- /* Enable low GPIO */
- val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
- val &= ~MOXA_GPIO_PIN2;
- outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
- }
-
- return num_ports;
-}
-
-static int
-pci_moxa_setup(struct serial_private *priv,
- const struct pciserial_board *board,
- struct uart_8250_port *port, int idx)
-{
- unsigned int bar = FL_GET_BASE(board->flags);
- int offset;
-
- if (!IS_ENABLED(CONFIG_HAS_IOPORT))
- return serial_8250_warn_need_ioport(priv->dev);
-
- if (board->num_ports == 4 && idx == 3)
- offset = 7 * board->uart_offset;
- else
- offset = idx * board->uart_offset;
-
- return setup_port(priv, port, bar, offset, 0);
-}
-
/*
* Master list of serial port init/setup/exit quirks.
* This does not describe the general nature of the port.
@@ -2931,17 +2780,6 @@ static struct pci_serial_quirk pci_serial_quirks[] = {
.setup = pci_fintek_setup,
.init = pci_fintek_init,
},
- /*
- * MOXA
- */
- {
- .vendor = PCI_VENDOR_ID_MOXA,
- .device = PCI_ANY_ID,
- .subvendor = PCI_ANY_ID,
- .subdevice = PCI_ANY_ID,
- .init = pci_moxa_init,
- .setup = pci_moxa_setup,
- },
{
.vendor = 0x1c29,
.device = 0x1204,
@@ -3159,9 +2997,6 @@ enum pci_board_num_t {
pbn_titan_2_4000000,
pbn_titan_4_4000000,
pbn_titan_8_4000000,
- pbn_moxa_2,
- pbn_moxa_4,
- pbn_moxa_8,
};
/*
@@ -3933,24 +3768,6 @@ static struct pciserial_board pci_boards[] = {
.uart_offset = 0x200,
.first_offset = 0x1000,
},
- [pbn_moxa_2] = {
- .flags = FL_BASE1,
- .num_ports = 2,
- .base_baud = 921600,
- .uart_offset = 0x200,
- },
- [pbn_moxa_4] = {
- .flags = FL_BASE1,
- .num_ports = 4,
- .base_baud = 921600,
- .uart_offset = 0x200,
- },
- [pbn_moxa_8] = {
- .flags = FL_BASE1,
- .num_ports = 8,
- .base_baud = 921600,
- .uart_offset = 0x200,
- },
};
#define REPORT_CONFIG(option) \
@@ -5811,28 +5628,6 @@ static const struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_4 },
- /*
- * MOXA
- */
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
-
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>
*/
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index e8b2878f8ab0..0db3ea0fd1d1 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -157,6 +157,17 @@ config SERIAL_8250_EXAR
422x PCIe serial cards that are not covered by the more generic
SERIAL_8250_PCI option.
+config SERIAL_8250_MOXA_PCIE
+ tristate "8250/16550 Moxa PCIe device support"
+ depends on SERIAL_8250 && PCI
+ select SERIAL_8250_PCILIB
+ default SERIAL_8250
+ help
+ Say Y here if you have a Moxa PCIe serial card.
+
+ To compile this driver as a module, choose M here: the
+ module will be called 8250_mxpcie.
+
config SERIAL_8250_MOXA_UPCI
tristate "8250/16550 Moxa UPCI device support"
depends on SERIAL_8250 && PCI
diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile
index da9d35911bd5..cf871a3a1fb7 100644
--- a/drivers/tty/serial/8250/Makefile
+++ b/drivers/tty/serial/8250/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
obj-$(CONFIG_SERIAL_8250_LPSS) += 8250_lpss.o
obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o
+obj-$(CONFIG_SERIAL_8250_MOXA_PCIE) += 8250_mxpcie.o
obj-$(CONFIG_SERIAL_8250_MOXA_UPCI) += 8250_mxupci.o
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci
2025-11-30 10:42 ` [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci Crescent Hsieh
@ 2025-11-30 19:22 ` Andy Shevchenko
2025-12-03 2:54 ` Crescent Hsieh
0 siblings, 1 reply; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 19:22 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
Thanks for the patch, my comments below.
> To avoid polluting 8250_pci, as suggested by Andy Shevchenko,
Suggested-by: tag?
> this patch
> separates 8250_mxpcie into its own module.
Imperative voice.
> - https://lore.kernel.org/all/ZmQovC6TbDpTb3c8@surfacebook.localdomain/
This can be made
Link: ... [1]
and referred to in the text as [1].
...
> + * 8250_mxpcie.c - Moxa PCIe multiport serial device driver
No filenames in the file, it makes it desynchronised in case of rename
as people often to forgot to update this.
...
> +#include <linux/module.h>
> +#include <linux/pci.h>
This needs more headers to be included
bitfield.h
bits.h
dev_printk.h
device/devres.h
ioport.h
types.h
...
> +static unsigned int mxpcie8250_get_supp_rs(unsigned short device)
> +{
> + switch (device & 0x0F00) {
GENMASK() ?
> + case 0x0000:
> + case 0x0600:
> + return MOXA_SUPP_RS232;
> + case 0x0100:
> + return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
> + case 0x0300:
> + return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
> + }
> +
> + return 0;
> +}
...
> + return FIELD_GET(0x00F0, device);
Define 0x00F0 with help of GENMASK() and use it here.
...
> +static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
> + unsigned int port_idx,
> + u8 mode)
> +{
> + resource_size_t iobar_addr = pci_resource_start(priv->pdev, 2);
> + resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
> + u8 cval;
> + cval = inb(UIR_addr);
I think it's in the original code, but can we switch to
ioreadXX()/iowriteXX() at some point?
> + if (port_idx % 2) {
> + cval &= ~MOXA_ODD_RS_MASK;
> + cval |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
FIELD_MODIFY()
> + } else {
> + cval &= ~MOXA_EVEN_RS_MASK;
> + cval |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
Ditto.
> + }
> + outb(cval, UIR_addr);
> +
> + return 0;
> +}
...
> +static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> +{
> + struct uart_8250_port up;
Can be just = {} and no memset() below is needed.
> + struct mxpcie8250 *priv;
> + unsigned int i, num_ports;
> + int ret;
> +
> + ret = pcim_enable_device(pdev);
> + pci_save_state(pdev);
Why here?
> +
If there is no need in the above, this blank line should be removed.
> + if (ret)
> + return ret;
> +
> + num_ports = mxpcie8250_get_nports(pdev->device);
> +
> + priv = devm_kzalloc(&pdev->dev, struct_size(priv, line, num_ports), GFP_KERNEL);
With
struct device *dev = &pdev->dev;
the probe code will look neater.
> +
stray blank line addition.
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->supp_rs = mxpcie8250_get_supp_rs(pdev->device);
> + priv->num_ports = num_ports;
> +
> + mxpcie8250_init(pdev);
> + priv->pdev = pdev;
> +
> + memset(&up, 0, sizeof(up));
> +
> + up.port.dev = &pdev->dev;
> + up.port.irq = pdev->irq;
> + up.port.uartclk = MOXA_PUART_BASE_BAUD * 16;
> + up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
> +
> + for (i = 0; i < num_ports; i++) {
> + if (mxpcie8250_setup(pdev, priv, &up, i))
> + break;
> +
> + dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
> + up.port.iobase, up.port.irq, up.port.iotype);
> +
> + priv->line[i] = serial8250_register_8250_port(&up);
> +
Stray blank line addition.
> + if (priv->line[i] < 0) {
> + dev_err(&pdev->dev,
> + "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
> + up.port.iobase, up.port.irq,
> + up.port.iotype, priv->line[i]);
> + break;
> + }
> + }
> + pci_set_drvdata(pdev, priv);
> +
> + return 0;
> +}
...
> +static const struct pci_device_id mxpcie8250_pci_ids[] = {
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A) },
> + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A) },
Too many spaces (or are they tabs?) before each of }:s.
> + { }
> +};
...
> +static struct pci_driver mxpcie8250_pci_driver = {
> + .name = "8250_mxpcie",
> + .id_table = mxpcie8250_pci_ids,
> + .probe = mxpcie8250_probe,
> + .remove = mxpcie8250_remove,
> +};
> +
This blank line...
> +module_pci_driver(mxpcie8250_pci_driver);
...should be here.
> +MODULE_AUTHOR("Moxa Inc.");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Moxa PCIe Multiport Serial Device Driver");
> +MODULE_DEVICE_TABLE(pci, mxpcie8250_pci_ids);
Move this to be closer to the ID table initialisation.
> +MODULE_IMPORT_NS("SERIAL_8250_PCI");
...
Shouldn't MOXA devices be blacklisted in PCI to avoid enumeration by PCI class?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci
2025-11-30 19:22 ` Andy Shevchenko
@ 2025-12-03 2:54 ` Crescent Hsieh
2025-12-03 9:18 ` Andy Shevchenko
0 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-12-03 2:54 UTC (permalink / raw)
To: Andy Shevchenko
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 09:22:20PM +0200, Andy Shevchenko wrote:
> On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
> <crescentcy.hsieh@moxa.com> wrote:
> > +#include <linux/module.h>
> > +#include <linux/pci.h>
>
> This needs more headers to be included
>
> bitfield.h
> bits.h
> dev_printk.h
> device/devres.h
> ioport.h
> types.h
May I ask a clarification: my understanding was to include headers only
when the corresponding symbols are directly used.
Is the intention here to avoid relying on implicit includes and to make
the driver’s dependencies explicit?
---
Sincerely,
Crescent Hsieh
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci
2025-12-03 2:54 ` Crescent Hsieh
@ 2025-12-03 9:18 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-03 9:18 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Wed, Dec 3, 2025 at 4:54 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
>
> On Sun, Nov 30, 2025 at 09:22:20PM +0200, Andy Shevchenko wrote:
> > On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
> > <crescentcy.hsieh@moxa.com> wrote:
> > > +#include <linux/module.h>
> > > +#include <linux/pci.h>
> >
> > This needs more headers to be included
> >
> > bitfield.h
> > bits.h
> > dev_printk.h
> > device/devres.h
> > ioport.h
> > types.h
>
> May I ask a clarification: my understanding was to include headers only
> when the corresponding symbols are directly used.
Yes, and that's what I have checked (I spent some time reading the
whole patch, but I might even miss something, so this list might be
not comprehensive).
> Is the intention here to avoid relying on implicit includes and to make
> the driver’s dependencies explicit?
Yes.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 10/31] serial: 8250: add MUEx50 UART configuration
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (8 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 09/31] serial: 8250: split 8250_mxpcie from 8250_pci Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 19:23 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 11/31] serial: 8250_mxpcie: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
` (20 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
The MUEx50 UART does not fully conform to PORT_16550A or other standard
UART configurations.
This patch introduces a new UART configuration to accurately represent
the MUEx50 hardware capabilities and applies it to Moxa PCIe serial
boards.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
s
---
drivers/tty/serial/8250/8250_mxpcie.c | 3 ++-
drivers/tty/serial/8250/8250_port.c | 8 ++++++++
include/uapi/linux/serial_core.h | 3 +++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 2e26307a9fee..f38684d11a90 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -207,7 +207,8 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.dev = &pdev->dev;
up.port.irq = pdev->irq;
up.port.uartclk = MOXA_PUART_BASE_BAUD * 16;
- up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+ up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ up.port.type = PORT_MUEX50;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 7d022315b3aa..38825bb80749 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -327,6 +327,14 @@ static const struct serial8250_config uart_config[] = {
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
+ [PORT_MUEX50] = {
+ .name = "Moxa MUEx50 UART",
+ .fifo_size = 128,
+ .tx_loadsz = 128,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+ .rxtrig_bytes = {15, 31, 63, 111},
+ .flags = UART_CAP_FIFO,
+ },
};
/* Uart divisor latch read */
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 49c2fcb2e24c..9410402721e4 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -103,6 +103,9 @@
/* Moxa MU860 UART */
#define PORT_MU860 65
+/* Moxa MUEx50 UART */
+#define PORT_MUEX50 66
+
/*Digi jsm */
#define PORT_JSM 69
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 10/31] serial: 8250: add MUEx50 UART configuration
2025-11-30 10:42 ` [PATCH v1 10/31] serial: 8250: add MUEx50 UART configuration Crescent Hsieh
@ 2025-11-30 19:23 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 19:23 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> The MUEx50 UART does not fully conform to PORT_16550A or other standard
> UART configurations.
Same Q, what are the differences?
> This patch introduces a new UART configuration to accurately represent
Imperative voice.
> the MUEx50 hardware capabilities and applies it to Moxa PCIe serial
> boards.
>
> Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
>
> s
Stray line.
> ---
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 11/31] serial: 8250_mxpcie: enable enhanced mode and custom FIFO trigger levels
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (9 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 10/31] serial: 8250: add MUEx50 UART configuration Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 19:25 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 12/31] serial: 8250_mxpcie: enable auto RTS/CTS flow control Crescent Hsieh
` (19 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add support for enabling enhanced mode and configuring custom FIFO
trigger levels on Moxa PCIe serial boards.
Enhanced mode is activated via EFR[4] and SFR[5], which is required to
access special function registers used for advanced features. Once
enhanced mode is enabled, custom TX/RX FIFO trigger levels and flow
control thresholds are configured through specific registers.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 47 +++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index f38684d11a90..39a178dc0519 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -36,6 +36,19 @@
#define MOXA_PUART_BASE_BAUD 921600
#define MOXA_PUART_OFFSET 0x200
+/* Special Function Register (SFR) */
+#define MOXA_PUART_SFR 0x07
+#define MOXA_PUART_SFR_950 BIT(5)
+
+/* Enhanced Function Register (EFR) */
+#define MOXA_PUART_EFR 0x0A
+#define MOXA_PUART_EFR_ENHANCED BIT(4)
+
+#define MOXA_PUART_TTL 0x10 /* Tx Interrupt Trigger Level */
+#define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */
+#define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */
+#define MOXA_PUART_FCH 0x13 /* Flow Control High Trigger Level */
+
#define MOXA_GPIO_DIRECTION 0x09
#define MOXA_GPIO_OUTPUT 0x0A
@@ -124,6 +137,37 @@ static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
return 0;
}
+static int mxpcie8250_startup(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ int i, ret;
+
+ ret = serial8250_do_startup(port);
+
+ for (i = 0; i < 5; ++i)
+ serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
+
+ serial_out(up, MOXA_PUART_EFR, MOXA_PUART_EFR_ENHANCED);
+ serial_out(up, MOXA_PUART_SFR, MOXA_PUART_SFR_950);
+
+ serial_out(up, MOXA_PUART_TTL, 0);
+ serial_out(up, MOXA_PUART_RTL, 96);
+ serial_out(up, MOXA_PUART_FCL, 16);
+ serial_out(up, MOXA_PUART_FCH, 110);
+
+ return ret;
+}
+
+static void mxpcie8250_shutdown(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+
+ serial_out(up, MOXA_PUART_EFR, 0);
+ serial_out(up, MOXA_PUART_SFR, 0);
+
+ serial8250_do_shutdown(port);
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -210,6 +254,9 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
up.port.type = PORT_MUEX50;
+ up.port.startup = mxpcie8250_startup;
+ up.port.shutdown = mxpcie8250_shutdown;
+
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
break;
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 11/31] serial: 8250_mxpcie: enable enhanced mode and custom FIFO trigger levels
2025-11-30 10:42 ` [PATCH v1 11/31] serial: 8250_mxpcie: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
@ 2025-11-30 19:25 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-11-30 19:25 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add support for enabling enhanced mode and configuring custom FIFO
> trigger levels on Moxa PCIe serial boards.
>
> Enhanced mode is activated via EFR[4] and SFR[5], which is required to
> access special function registers used for advanced features. Once
> enhanced mode is enabled, custom TX/RX FIFO trigger levels and flow
> control thresholds are configured through specific registers.
...
> +static int mxpcie8250_startup(struct uart_port *port)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + int i, ret;
Should "i" be signed?
> + ret = serial8250_do_startup(port);
Same Q here: Why do we continue if we know it failed already?
> + for (i = 0; i < 5; ++i)
> + serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
> +
> + serial_out(up, MOXA_PUART_EFR, MOXA_PUART_EFR_ENHANCED);
> + serial_out(up, MOXA_PUART_SFR, MOXA_PUART_SFR_950);
> +
> + serial_out(up, MOXA_PUART_TTL, 0);
> + serial_out(up, MOXA_PUART_RTL, 96);
> + serial_out(up, MOXA_PUART_FCL, 16);
> + serial_out(up, MOXA_PUART_FCH, 110);
> +
> + return ret;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 12/31] serial: 8250_mxpcie: enable auto RTS/CTS flow control
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (10 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 11/31] serial: 8250_mxpcie: enable enhanced mode and custom FIFO trigger levels Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 13/31] serial: 8250_mxpcie: enable on-chip software " Crescent Hsieh
` (18 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Implement a custom set_termios() to configure RTS/CTS hardware flow
control using the Enhanced Feature Register (EFR). This enables support
for automatic RTS/CTS signaling when CRTSCTS is enabled in termios.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 39a178dc0519..197d016354c9 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -43,6 +43,10 @@
/* Enhanced Function Register (EFR) */
#define MOXA_PUART_EFR 0x0A
#define MOXA_PUART_EFR_ENHANCED BIT(4)
+#define MOXA_PUART_EFR_AUTO_RTS BIT(6)
+#define MOXA_PUART_EFR_AUTO_CTS BIT(7)
+#define MOXA_PUART_EFR_RX_FLOW_MASK GENMASK(1, 0)
+#define MOXA_PUART_EFR_TX_FLOW_MASK GENMASK(3, 2)
#define MOXA_PUART_TTL 0x10 /* Tx Interrupt Trigger Level */
#define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */
@@ -137,6 +141,29 @@ static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
return 0;
}
+static void mxpcie8250_set_termios(struct uart_port *port,
+ struct ktermios *new,
+ const struct ktermios *old)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int cflag = tty->termios.c_cflag;
+ u8 efr;
+
+ serial8250_do_set_termios(port, new, old);
+
+ up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+
+ efr = serial_in(up, MOXA_PUART_EFR);
+ efr &= ~(MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS);
+
+ if (cflag & CRTSCTS) {
+ efr |= (MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS);
+ up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+ }
+ serial_out(up, MOXA_PUART_EFR, efr);
+}
+
static int mxpcie8250_startup(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -254,6 +281,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
up.port.type = PORT_MUEX50;
+ up.port.set_termios = mxpcie8250_set_termios;
up.port.startup = mxpcie8250_startup;
up.port.shutdown = mxpcie8250_shutdown;
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 13/31] serial: 8250_mxpcie: enable on-chip software flow control
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (11 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 12/31] serial: 8250_mxpcie: enable auto RTS/CTS flow control Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 14/31] serial: 8250_mxpcie: add custom handle_irq() Crescent Hsieh
` (17 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Enable on-chip XON/XOFF software flow control via EFR[3:0], and configure
XON/XOFF characters using dedicated registers.
This patch also implements throttle() and unthrottle() to handle receive
pause and resume based on software flow control.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 62 ++++++++++++++++++++++++++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 197d016354c9..ceef6a5e677e 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -41,13 +41,31 @@
#define MOXA_PUART_SFR_950 BIT(5)
/* Enhanced Function Register (EFR) */
+/*
+ * EFR[1:0] - In-Band Receive Flow Control Mode (Compare XON/XOFF):
+ * 00b (0x00) = Disabled
+ * 01b (0x01) = Recognize XON2 & XOFF2 as XOFF character
+ * 10b (0x02) = Recognize XON1 & XOFF1 as XOFF character
+ * 11b (0x03) = Depends on EFR[3:2]
+ * EFR[3:2] - In-Band Transmit Flow Control Mode (Insert XON/XOFF):
+ * 00b (0x00) = Disabled
+ * 01b (0x04) = Use XON2 & XOFF2 as XOFF character
+ * 10b (0x08) = Use XON1 & XOFF1 as XOFF character
+ * 11b (0x0C) = Reserved
+ */
#define MOXA_PUART_EFR 0x0A
+#define MOXA_PUART_EFR_RX_FLOW 0x02 /* Recognize XON1 & XOFF1 as XOFF character */
+#define MOXA_PUART_EFR_TX_FLOW 0x08 /* Use XON1 & XOFF1 as XOFF character */
#define MOXA_PUART_EFR_ENHANCED BIT(4)
#define MOXA_PUART_EFR_AUTO_RTS BIT(6)
#define MOXA_PUART_EFR_AUTO_CTS BIT(7)
#define MOXA_PUART_EFR_RX_FLOW_MASK GENMASK(1, 0)
#define MOXA_PUART_EFR_TX_FLOW_MASK GENMASK(3, 2)
+#define MOXA_PUART_XON1 0x0B
+#define MOXA_PUART_XON2 0x0C
+#define MOXA_PUART_XOFF1 0x0D
+#define MOXA_PUART_XOFF2 0x0E
#define MOXA_PUART_TTL 0x10 /* Tx Interrupt Trigger Level */
#define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */
#define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */
@@ -152,7 +170,7 @@ static void mxpcie8250_set_termios(struct uart_port *port,
serial8250_do_set_termios(port, new, old);
- up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
+ up->port.status &= ~(UPSTAT_AUTORTS | UPSTAT_AUTOCTS | UPSTAT_AUTOXOFF);
efr = serial_in(up, MOXA_PUART_EFR);
efr &= ~(MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS);
@@ -161,6 +179,21 @@ static void mxpcie8250_set_termios(struct uart_port *port,
efr |= (MOXA_PUART_EFR_AUTO_RTS | MOXA_PUART_EFR_AUTO_CTS);
up->port.status |= (UPSTAT_AUTORTS | UPSTAT_AUTOCTS);
}
+ /* Set on-chip software flow control character */
+ serial_out(up, MOXA_PUART_XON1, START_CHAR(tty));
+ serial_out(up, MOXA_PUART_XON2, START_CHAR(tty));
+ serial_out(up, MOXA_PUART_XOFF1, STOP_CHAR(tty));
+ serial_out(up, MOXA_PUART_XOFF2, STOP_CHAR(tty));
+
+ efr &= ~(MOXA_PUART_EFR_RX_FLOW_MASK | MOXA_PUART_EFR_TX_FLOW_MASK);
+
+ if (I_IXON(tty))
+ efr |= MOXA_PUART_EFR_RX_FLOW;
+
+ if (I_IXOFF(tty)) {
+ efr |= MOXA_PUART_EFR_TX_FLOW;
+ up->port.status |= UPSTAT_AUTOXOFF;
+ }
serial_out(up, MOXA_PUART_EFR, efr);
}
@@ -195,6 +228,31 @@ static void mxpcie8250_shutdown(struct uart_port *port)
serial8250_do_shutdown(port);
}
+static void mxpcie8250_throttle(struct uart_port *port)
+{
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ port->ops->stop_rx(port);
+
+ uart_port_unlock_irqrestore(port, flags);
+}
+
+static void mxpcie8250_unthrottle(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ up->ier |= UART_IER_RLSI | UART_IER_RDI;
+ port->read_status_mask |= UART_LSR_DR;
+ serial_out(up, UART_IER, up->ier);
+
+ uart_port_unlock_irqrestore(port, flags);
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -284,6 +342,8 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.set_termios = mxpcie8250_set_termios;
up.port.startup = mxpcie8250_startup;
up.port.shutdown = mxpcie8250_shutdown;
+ up.port.throttle = mxpcie8250_throttle;
+ up.port.unthrottle = mxpcie8250_unthrottle;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 14/31] serial: 8250_mxpcie: add custom handle_irq()
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (12 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 13/31] serial: 8250_mxpcie: enable on-chip software " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:40 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 15/31] serial: 8250_mxpcie: optimize Rx using memory-mapped FIFO access Crescent Hsieh
` (16 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add a custom handle_irq() for 8250_mxpcie based on serial8250_handle_irq(),
removing PM wakeup and DMA handling that are not needed.
This prepares for future adjustments to RX and TX behavior specific to
Moxa MUEx50 UART.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 36 +++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index ceef6a5e677e..fe2906d16d80 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -253,6 +253,41 @@ static void mxpcie8250_unthrottle(struct uart_port *port)
uart_port_unlock_irqrestore(port, flags);
}
+static int mxpcie8250_handle_irq(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ bool skip_rx = false;
+ unsigned long flags;
+ u16 lsr;
+ u8 iir;
+
+ iir = serial_in(up, UART_IIR);
+
+ if (iir & UART_IIR_NO_INT)
+ return 0;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ lsr = serial_lsr_in(up);
+
+ if (!(lsr & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
+ (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
+ !(port->read_status_mask & UART_LSR_DR))
+ skip_rx = true;
+
+ if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
+ lsr = serial8250_rx_chars(up, lsr);
+
+ serial8250_modem_status(up);
+
+ if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
+ serial8250_tx_chars(up);
+
+ uart_unlock_and_check_sysrq_irqrestore(port, flags);
+
+ return 1;
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -344,6 +379,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.shutdown = mxpcie8250_shutdown;
up.port.throttle = mxpcie8250_throttle;
up.port.unthrottle = mxpcie8250_unthrottle;
+ up.port.handle_irq = mxpcie8250_handle_irq;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 14/31] serial: 8250_mxpcie: add custom handle_irq()
2025-11-30 10:42 ` [PATCH v1 14/31] serial: 8250_mxpcie: add custom handle_irq() Crescent Hsieh
@ 2025-12-01 1:40 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:40 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add a custom handle_irq() for 8250_mxpcie based on serial8250_handle_irq(),
> removing PM wakeup and DMA handling that are not needed.
>
> This prepares for future adjustments to RX and TX behavior specific to
> Moxa MUEx50 UART.
...
> +static int mxpcie8250_handle_irq(struct uart_port *port)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + bool skip_rx = false;
> + unsigned long flags;
> + u16 lsr;
> + u8 iir;
> +
> + iir = serial_in(up, UART_IIR);
> +
Unneeded blank line.
> + if (iir & UART_IIR_NO_INT)
> + return 0;
> +
> + uart_port_lock_irqsave(port, &flags);
> +
> + lsr = serial_lsr_in(up);
> +
Ditto.
> + if (!(lsr & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
> + (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
> + !(port->read_status_mask & UART_LSR_DR))
> + skip_rx = true;
> +
> + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> + lsr = serial8250_rx_chars(up, lsr);
Again, perhaps it's better to split the above to a few if-return
conditionals in a local helper.
> + serial8250_modem_status(up);
> +
> + if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
> + serial8250_tx_chars(up);
> +
> + uart_unlock_and_check_sysrq_irqrestore(port, flags);
> +
> + return 1;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 15/31] serial: 8250_mxpcie: optimize Rx using memory-mapped FIFO access
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (13 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 14/31] serial: 8250_mxpcie: add custom handle_irq() Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:43 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 16/31] serial: 8250_mxpcie: optimize Tx " Crescent Hsieh
` (15 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add mxpcie8250_rx_chars() to retrieve data from the Rx FIFO via
memory-mapped FIFO access, using the UART-specific FIFO byte counter
and FIFO memory region.
This avoids per-byte I/O reads through serial_in(), improving receive
throughput on Moxa PCIe UART devices. For break and error conditions,
the handler falls back to serial8250_rx_chars() to retain standard
error handling logic.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 37 +++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index fe2906d16d80..cf519960d5d1 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -8,6 +8,7 @@
#include <linux/module.h>
#include <linux/pci.h>
+#include <linux/tty_flip.h>
#include <linux/8250_pci.h>
#include "8250.h"
@@ -35,6 +36,7 @@
/* UART */
#define MOXA_PUART_BASE_BAUD 921600
#define MOXA_PUART_OFFSET 0x200
+#define MOXA_PUART_FIFO_SIZE 128
/* Special Function Register (SFR) */
#define MOXA_PUART_SFR 0x07
@@ -70,6 +72,9 @@
#define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */
#define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */
#define MOXA_PUART_FCH 0x13 /* Flow Control High Trigger Level */
+#define MOXA_PUART_RX_FIFO_CNT 0x15 /* Rx FIFO Data Counter */
+
+#define MOXA_PUART_RX_FIFO_MEM 0x100 /* Memory Space to Rx FIFO Data Register */
#define MOXA_GPIO_DIRECTION 0x09
#define MOXA_GPIO_OUTPUT 0x0A
@@ -253,6 +258,30 @@ static void mxpcie8250_unthrottle(struct uart_port *port)
uart_port_unlock_irqrestore(port, flags);
}
+static void mxpcie8250_rx_chars(struct uart_8250_port *up)
+{
+ struct uart_port *port = &up->port;
+ struct tty_port *tport = &port->state->port;
+ int recv_room, gdl, i;
+ u8 buf[MOXA_PUART_FIFO_SIZE];
+
+ recv_room = tty_buffer_request_room(tport, port->fifosize);
+
+ if (recv_room) {
+ gdl = serial_in(up, MOXA_PUART_RX_FIFO_CNT);
+
+ if (gdl > recv_room)
+ gdl = recv_room;
+
+ for (i = 0; i < gdl; ++i)
+ buf[i] = *(port->membase + MOXA_PUART_RX_FIFO_MEM + i);
+
+ port->icount.rx += gdl;
+ tty_insert_flip_string(tport, buf, gdl);
+ tty_flip_buffer_push(tport);
+ }
+}
+
static int mxpcie8250_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -275,8 +304,12 @@ static int mxpcie8250_handle_irq(struct uart_port *port)
!(port->read_status_mask & UART_LSR_DR))
skip_rx = true;
- if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
- lsr = serial8250_rx_chars(up, lsr);
+ if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
+ if (lsr & UART_LSR_BRK_ERROR_BITS)
+ lsr = serial8250_rx_chars(up, lsr);
+ else
+ mxpcie8250_rx_chars(up);
+ }
serial8250_modem_status(up);
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 15/31] serial: 8250_mxpcie: optimize Rx using memory-mapped FIFO access
2025-11-30 10:42 ` [PATCH v1 15/31] serial: 8250_mxpcie: optimize Rx using memory-mapped FIFO access Crescent Hsieh
@ 2025-12-01 1:43 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:43 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add mxpcie8250_rx_chars() to retrieve data from the Rx FIFO via
> memory-mapped FIFO access, using the UART-specific FIFO byte counter
> and FIFO memory region.
>
> This avoids per-byte I/O reads through serial_in(), improving receive
> throughput on Moxa PCIe UART devices. For break and error conditions,
> the handler falls back to serial8250_rx_chars() to retain standard
> error handling logic.
...
> +static void mxpcie8250_rx_chars(struct uart_8250_port *up)
> +{
> + struct uart_port *port = &up->port;
> + struct tty_port *tport = &port->state->port;
> + int recv_room, gdl, i;
> + u8 buf[MOXA_PUART_FIFO_SIZE];
> +
> + recv_room = tty_buffer_request_room(tport, port->fifosize);
> +
Unneeded blank line
> + if (recv_room) {
if (!recv_room)
return;
> + gdl = serial_in(up, MOXA_PUART_RX_FIFO_CNT);
> +
Unneeded blank line.
> + if (gdl > recv_room)
> + gdl = recv_room;
> + for (i = 0; i < gdl; ++i)
> + buf[i] = *(port->membase + MOXA_PUART_RX_FIFO_MEM + i);
> +
> + port->icount.rx += gdl;
> + tty_insert_flip_string(tport, buf, gdl);
> + tty_flip_buffer_push(tport);
> + }
> +}
...
> - if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx)
> - lsr = serial8250_rx_chars(up, lsr);
> + if (lsr & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
> + if (lsr & UART_LSR_BRK_ERROR_BITS)
> + lsr = serial8250_rx_chars(up, lsr);
> + else
> + mxpcie8250_rx_chars(up);
> + }
And again, please try not to modify the code you just added in the
previous changes.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 16/31] serial: 8250_mxpcie: optimize Tx using memory-mapped FIFO access
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (14 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 15/31] serial: 8250_mxpcie: optimize Rx using memory-mapped FIFO access Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:52 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 17/31] serial: 8250_mxpcie: enable serial interface switching Crescent Hsieh
` (14 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add mxpcie8250_tx_chars() to transmit data via memory-mapped FIFO
access, using the UART-specific Tx FIFO counter and buffer region.
This replaces serial8250_tx_chars() to reduce per-byte I/O operations
and improve transmit throughput on Moxa PCIe UART devices.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 35 ++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index cf519960d5d1..90ce522fe40f 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -73,8 +73,10 @@
#define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */
#define MOXA_PUART_FCH 0x13 /* Flow Control High Trigger Level */
#define MOXA_PUART_RX_FIFO_CNT 0x15 /* Rx FIFO Data Counter */
+#define MOXA_PUART_TX_FIFO_CNT 0x16 /* Tx FIFO Data Counter */
#define MOXA_PUART_RX_FIFO_MEM 0x100 /* Memory Space to Rx FIFO Data Register */
+#define MOXA_PUART_TX_FIFO_MEM 0x100 /* Memory Space to Tx FIFO Data Register */
#define MOXA_GPIO_DIRECTION 0x09
#define MOXA_GPIO_OUTPUT 0x0A
@@ -282,6 +284,37 @@ static void mxpcie8250_rx_chars(struct uart_8250_port *up)
}
}
+static void mxpcie8250_tx_chars(struct uart_8250_port *up)
+{
+ struct uart_port *port = &up->port;
+ struct tty_port *tport = &port->state->port;
+ unsigned int count, i;
+ unsigned char c;
+
+ if (port->x_char) {
+ uart_xchar_out(port, UART_TX);
+ return;
+ }
+ if (uart_tx_stopped(port) || kfifo_is_empty(&tport->xmit_fifo)) {
+ port->ops->stop_tx(port);
+ return;
+ }
+ count = kfifo_len(&tport->xmit_fifo);
+ count = min(count, port->fifosize - serial_in(up, MOXA_PUART_TX_FIFO_CNT));
+
+ for (i = 0; i < count; ++i) {
+ if (!uart_fifo_get(port, &c))
+ break;
+
+ *(port->membase + MOXA_PUART_TX_FIFO_MEM + i) = c;
+ }
+ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (kfifo_is_empty(&tport->xmit_fifo) && !(up->capabilities & UART_CAP_RPM))
+ port->ops->stop_tx(port);
+}
+
static int mxpcie8250_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -314,7 +347,7 @@ static int mxpcie8250_handle_irq(struct uart_port *port)
serial8250_modem_status(up);
if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
- serial8250_tx_chars(up);
+ mxpcie8250_tx_chars(up);
uart_unlock_and_check_sysrq_irqrestore(port, flags);
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 16/31] serial: 8250_mxpcie: optimize Tx using memory-mapped FIFO access
2025-11-30 10:42 ` [PATCH v1 16/31] serial: 8250_mxpcie: optimize Tx " Crescent Hsieh
@ 2025-12-01 1:52 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:52 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:44 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Add mxpcie8250_tx_chars() to transmit data via memory-mapped FIFO
> access, using the UART-specific Tx FIFO counter and buffer region.
>
> This replaces serial8250_tx_chars() to reduce per-byte I/O operations
> and improve transmit throughput on Moxa PCIe UART devices.
...
> +static void mxpcie8250_tx_chars(struct uart_8250_port *up)
> +{
> + struct uart_port *port = &up->port;
> + struct tty_port *tport = &port->state->port;
> + unsigned int count, i;
> + unsigned char c;
> +
> + if (port->x_char) {
> + uart_xchar_out(port, UART_TX);
> + return;
> + }
> + if (uart_tx_stopped(port) || kfifo_is_empty(&tport->xmit_fifo)) {
> + port->ops->stop_tx(port);
> + return;
> + }
> + count = kfifo_len(&tport->xmit_fifo);
> + count = min(count, port->fifosize - serial_in(up, MOXA_PUART_TX_FIFO_CNT));
Perhaps
unsigned int i, count, txsize;
...
txsize = serial_in(up, MOXA_PUART_TX_FIFO_CNT);
count = min(kfifo_len(...), fifosize - txsize);
?
> + for (i = 0; i < count; ++i) {
> + if (!uart_fifo_get(port, &c))
> + break;
> + *(port->membase + MOXA_PUART_TX_FIFO_MEM + i) = c;
This is interesting... Why can't the proper IO accessors be used?
> + }
> + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
> + uart_write_wakeup(port);
> +
> + if (kfifo_is_empty(&tport->xmit_fifo) && !(up->capabilities & UART_CAP_RPM))
> + port->ops->stop_tx(port);
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 17/31] serial: 8250_mxpcie: enable serial interface switching
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (15 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 16/31] serial: 8250_mxpcie: optimize Tx " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 18/31] serial: 8250: allow low-level driver to override break_ctl() Crescent Hsieh
` (13 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Add support for Moxa PCIe multiport serial boards to switch serial
interfaces via the ioctl() command "TIOCSRS485" using the following
flags in the "serial_rs485" struct:
- RS232 = (no flags set)
- RS422 = SER_RS485_ENABLED | SER_RS485_MODE_RS422
- RS485_2W (half-duplex) = SER_RS485_ENABLED
- RS485_4W (full-duplex) = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX
This allows users to dynamically configure the serial mode without
requiring additional hardware modifications.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 45 +++++++++++++++++++++++++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 90ce522fe40f..5d1097c166e4 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -105,6 +105,10 @@ enum {
MOXA_SUPP_RS485 = BIT(2),
};
+static const struct serial_rs485 mxpcie8250_rs485_supported = {
+ .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | SER_RS485_MODE_RS422,
+};
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
@@ -166,6 +170,38 @@ static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
return 0;
}
+/*
+ * Moxa PCIe multiport serial boards support switching serial interfaces
+ * via the ioctl() command "TIOCSRS485". Supported modes and corresponding
+ * flags in "serial_rs485":
+ *
+ * RS232 = (no flags set)
+ * RS422 = SER_RS485_ENABLED | SER_RS485_MODE_RS422
+ * RS485_2W (half-duplex) = SER_RS485_ENABLED
+ * RS485_4W (full-duplex) = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX
+ */
+static int mxpcie8250_rs485_config(struct uart_port *port,
+ struct ktermios *termios,
+ struct serial_rs485 *rs485)
+{
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ u8 mode = MOXA_UIR_RS232;
+
+ if (rs485->flags & SER_RS485_ENABLED) {
+ if (rs485->flags & SER_RS485_MODE_RS422)
+ mode = MOXA_UIR_RS422;
+ else if (rs485->flags & SER_RS485_RX_DURING_TX)
+ mode = MOXA_UIR_RS485_4W;
+ else
+ mode = MOXA_UIR_RS485_2W;
+ } else if (!(priv->supp_rs & MOXA_SUPP_RS232)) {
+ return -ENODEV;
+ }
+
+ return mxpcie8250_set_interface(priv, port->port_id, mode);
+}
+
static void mxpcie8250_set_termios(struct uart_port *port,
struct ktermios *new,
const struct ktermios *old)
@@ -392,9 +428,14 @@ static int mxpcie8250_setup(struct pci_dev *pdev,
int offset = idx * MOXA_PUART_OFFSET;
u8 init_mode = MOXA_UIR_RS232;
- if (!(priv->supp_rs & MOXA_SUPP_RS232))
+ if (priv->supp_rs & MOXA_SUPP_RS485) {
+ up->port.rs485_config = mxpcie8250_rs485_config;
+ up->port.rs485_supported = mxpcie8250_rs485_supported;
+ }
+ if (!(priv->supp_rs & MOXA_SUPP_RS232)) {
init_mode = MOXA_UIR_RS422;
-
+ up->port.rs485.flags = SER_RS485_ENABLED | SER_RS485_MODE_RS422;
+ }
mxpcie8250_set_interface(priv, idx, init_mode);
if (idx == 3 &&
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 18/31] serial: 8250: allow low-level driver to override break_ctl()
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (16 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 17/31] serial: 8250_mxpcie: enable serial interface switching Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:54 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 19/31] serial: 8250_mxpcie: add break signal support under RS485 Crescent Hsieh
` (12 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Moxa PCIe serial boards requires custom break signal transmission under
RS485 mdoe. However, the current 8250 driver does not provide a way for
low-level driver to override this behavior.
This patch introduces a break_ctl() function pointer in struct
uart_port, allowing low-level drivers to customize the break signal
transmission logic. If no custom implementation is provided, the default
serial8250_do_break_ctl() function is used. This ensures that
hardware-specific break signaling can be implemented without affecting
standard behavior.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_core.c | 2 ++
drivers/tty/serial/8250/8250_port.c | 11 ++++++++++-
include/linux/serial_8250.h | 1 +
include/linux/serial_core.h | 1 +
4 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 68baf75bdadc..f642e8c77911 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -802,6 +802,8 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
uart->port.startup = up->port.startup;
if (up->port.shutdown)
uart->port.shutdown = up->port.shutdown;
+ if (up->port.break_ctl)
+ uart->port.break_ctl = up->port.break_ctl;
if (up->port.pm)
uart->port.pm = up->port.pm;
if (up->port.handle_break)
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 38825bb80749..64896f37b75d 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -2079,7 +2079,7 @@ static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
serial8250_do_set_mctrl(port, mctrl);
}
-static void serial8250_break_ctl(struct uart_port *port, int break_state)
+void serial8250_do_break_ctl(struct uart_port *port, int break_state)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
@@ -2094,6 +2094,15 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state)
uart_port_unlock_irqrestore(port, flags);
serial8250_rpm_put(up);
}
+EXPORT_SYMBOL_GPL(serial8250_do_break_ctl);
+
+static void serial8250_break_ctl(struct uart_port *port, int break_state)
+{
+ if (port->break_ctl)
+ port->break_ctl(port, break_state);
+ else
+ serial8250_do_break_ctl(port, break_state);
+}
static void wait_for_lsr(struct uart_8250_port *up, int bits)
{
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index e0717c8393d7..88996a3194de 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -192,6 +192,7 @@ void serial8250_do_shutdown(struct uart_port *port);
void serial8250_do_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate);
void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl);
+void serial8250_do_break_ctl(struct uart_port *port, int break_state);
void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
unsigned int quot);
int fsl8250_handle_irq(struct uart_port *port);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 743b4afaad4c..1aa07c5187d8 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -451,6 +451,7 @@ struct uart_port {
void (*shutdown)(struct uart_port *port);
void (*throttle)(struct uart_port *port);
void (*unthrottle)(struct uart_port *port);
+ void (*break_ctl)(struct uart_port *port, int break_state);
int (*handle_irq)(struct uart_port *);
void (*pm)(struct uart_port *, unsigned int state,
unsigned int old);
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 18/31] serial: 8250: allow low-level driver to override break_ctl()
2025-11-30 10:42 ` [PATCH v1 18/31] serial: 8250: allow low-level driver to override break_ctl() Crescent Hsieh
@ 2025-12-01 1:54 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:54 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Moxa PCIe serial boards requires custom break signal transmission under
> RS485 mdoe. However, the current 8250 driver does not provide a way for
mode
> low-level driver to override this behavior.
>
> This patch introduces a break_ctl() function pointer in struct
> uart_port, allowing low-level drivers to customize the break signal
> transmission logic. If no custom implementation is provided, the default
> serial8250_do_break_ctl() function is used. This ensures that
> hardware-specific break signaling can be implemented without affecting
> standard behavior.
...
> +EXPORT_SYMBOL_GPL(serial8250_do_break_ctl);
There is another (scoped) export used in this driver, use it for this
function as well.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 19/31] serial: 8250_mxpcie: add break signal support under RS485
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (17 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 18/31] serial: 8250: allow low-level driver to override break_ctl() Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:56 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 20/31] serial: 8250: add optional callbacks for rx_trig_bytes Crescent Hsieh
` (11 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Moxa PCIe boards require a specific sequence to send break signals in
RS485 mode. This patch implements the required behavior, while falling
back to the default break mechanism in RS232 and RS422 modes.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 52 +++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 5d1097c166e4..9ba171274221 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -40,6 +40,7 @@
/* Special Function Register (SFR) */
#define MOXA_PUART_SFR 0x07
+#define MOXA_PUART_SFR_FORCE_TX BIT(0)
#define MOXA_PUART_SFR_950 BIT(5)
/* Enhanced Function Register (EFR) */
@@ -390,6 +391,56 @@ static int mxpcie8250_handle_irq(struct uart_port *port)
return 1;
}
+static void mxpcie8250_software_break_ctl(struct uart_port *port, int break_state)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned char tx_byte = 0x01;
+ unsigned int baud, quot;
+ unsigned long flags;
+ u8 sfr;
+
+ uart_port_lock_irqsave(port, &flags);
+
+ if (break_state == -1) {
+ serial_out(up, UART_LCR, up->lcr | UART_LCR_DLAB);
+ serial_out(up, UART_DLL, 0);
+ serial_out(up, UART_DLM, 0);
+ serial_out(up, UART_LCR, up->lcr);
+
+ memcpy(port->membase + MOXA_PUART_TX_FIFO_MEM, &tx_byte, 1);
+
+ sfr = serial_in(up, MOXA_PUART_SFR);
+ serial_out(up, MOXA_PUART_SFR, sfr | MOXA_PUART_SFR_FORCE_TX);
+
+ up->lcr |= UART_LCR_SBC;
+ serial_out(up, UART_LCR, up->lcr);
+ } else {
+ up->lcr &= ~UART_LCR_SBC;
+ serial_out(up, UART_LCR, up->lcr);
+
+ sfr = serial_in(up, MOXA_PUART_SFR);
+ serial_out(up, MOXA_PUART_SFR, sfr &= ~MOXA_PUART_SFR_FORCE_TX);
+
+ serial_out(up, UART_FCR, UART_FCR_CLEAR_XMIT);
+
+ baud = tty_get_baud_rate(tty);
+ quot = uart_get_divisor(port, baud);
+ serial8250_do_set_divisor(port, baud, quot);
+ serial_out(up, UART_LCR, up->lcr);
+ }
+ uart_port_unlock_irqrestore(port, flags);
+}
+
+static void mxpcie8250_break_ctl(struct uart_port *port, int break_state)
+{
+ if (port->rs485.flags & SER_RS485_ENABLED &&
+ !(port->rs485.flags & SER_RS485_MODE_RS422))
+ mxpcie8250_software_break_ctl(port, break_state);
+ else
+ serial8250_do_break_ctl(port, break_state);
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -487,6 +538,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.throttle = mxpcie8250_throttle;
up.port.unthrottle = mxpcie8250_unthrottle;
up.port.handle_irq = mxpcie8250_handle_irq;
+ up.port.break_ctl = mxpcie8250_break_ctl;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 19/31] serial: 8250_mxpcie: add break signal support under RS485
2025-11-30 10:42 ` [PATCH v1 19/31] serial: 8250_mxpcie: add break signal support under RS485 Crescent Hsieh
@ 2025-12-01 1:56 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:56 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Moxa PCIe boards require a specific sequence to send break signals in
> RS485 mode. This patch implements the required behavior, while falling
> back to the default break mechanism in RS232 and RS422 modes.
...
> +static void mxpcie8250_software_break_ctl(struct uart_port *port, int break_state)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + struct tty_struct *tty = port->state->port.tty;
> + unsigned char tx_byte = 0x01;
> + unsigned int baud, quot;
> + unsigned long flags;
> + u8 sfr;
> +
> + uart_port_lock_irqsave(port, &flags);
> +
> + if (break_state == -1) {
> + serial_out(up, UART_LCR, up->lcr | UART_LCR_DLAB);
> + serial_out(up, UART_DLL, 0);
> + serial_out(up, UART_DLM, 0);
> + serial_out(up, UART_LCR, up->lcr);
> + memcpy(port->membase + MOXA_PUART_TX_FIFO_MEM, &tx_byte, 1);
My gosh, why?
It's even different to the way you used in the previous change.
> + sfr = serial_in(up, MOXA_PUART_SFR);
> + serial_out(up, MOXA_PUART_SFR, sfr | MOXA_PUART_SFR_FORCE_TX);
> +
> + up->lcr |= UART_LCR_SBC;
> + serial_out(up, UART_LCR, up->lcr);
> + } else {
> + up->lcr &= ~UART_LCR_SBC;
> + serial_out(up, UART_LCR, up->lcr);
> +
> + sfr = serial_in(up, MOXA_PUART_SFR);
> + serial_out(up, MOXA_PUART_SFR, sfr &= ~MOXA_PUART_SFR_FORCE_TX);
> +
> + serial_out(up, UART_FCR, UART_FCR_CLEAR_XMIT);
> +
> + baud = tty_get_baud_rate(tty);
> + quot = uart_get_divisor(port, baud);
> + serial8250_do_set_divisor(port, baud, quot);
> + serial_out(up, UART_LCR, up->lcr);
> + }
> + uart_port_unlock_irqrestore(port, flags);
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 20/31] serial: 8250: add optional callbacks for rx_trig_bytes
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (18 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 19/31] serial: 8250_mxpcie: add break signal support under RS485 Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 1:58 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 21/31] serial: 8250_mxpcie: implement rx_trig_bytes callbacks and persist per-port level Crescent Hsieh
` (10 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
The rx_trig_bytes sysfs attribute adjusts the UART RX FIFO trigger
level. Some modern 8250 variants require programming device-specific
registers to change this threshold, which the generic (FCR-based) path
does not cover.
This patch adds two optional uart_port callbacks:
- set_rxtrig(port, bytes): program a device-specific RX trigger threshold
- get_rxtrig(port): read back the current RX trigger threshold
When these callbacks are provided, the 8250 core will use them to
set/read the hardware-specific threshold. If the callbacks are not
implemented, the code falls back to the legacy generic path, so existing
drivers keep their current behavior.
No functional change for drivers that do not implement the new
callbacks.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_core.c | 4 ++++
drivers/tty/serial/8250/8250_port.c | 16 ++++++++++++++--
include/linux/serial_core.h | 2 ++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index f642e8c77911..3d8575874759 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -808,6 +808,10 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
uart->port.pm = up->port.pm;
if (up->port.handle_break)
uart->port.handle_break = up->port.handle_break;
+ if (up->port.set_rxtrig)
+ uart->port.set_rxtrig = up->port.set_rxtrig;
+ if (up->port.get_rxtrig)
+ uart->port.get_rxtrig = up->port.get_rxtrig;
if (up->dl_read)
uart->dl_read = up->dl_read;
if (up->dl_write)
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 64896f37b75d..d7baceacd4ff 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -3104,9 +3104,15 @@ static ssize_t rx_trig_bytes_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct tty_port *port = dev_get_drvdata(dev);
+ struct uart_state *state = container_of(port, struct uart_state, port);
+ struct uart_port *uport = state->uart_port;
int rxtrig_bytes;
- rxtrig_bytes = do_serial8250_get_rxtrig(port);
+ if (uport->get_rxtrig)
+ rxtrig_bytes = uport->get_rxtrig(uport);
+ else
+ rxtrig_bytes = do_serial8250_get_rxtrig(port);
+
if (rxtrig_bytes < 0)
return rxtrig_bytes;
@@ -3149,6 +3155,8 @@ static ssize_t rx_trig_bytes_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct tty_port *port = dev_get_drvdata(dev);
+ struct uart_state *state = container_of(port, struct uart_state, port);
+ struct uart_port *uport = state->uart_port;
unsigned char bytes;
int ret;
@@ -3159,7 +3167,11 @@ static ssize_t rx_trig_bytes_store(struct device *dev,
if (ret < 0)
return ret;
- ret = do_serial8250_set_rxtrig(port, bytes);
+ if (uport->set_rxtrig)
+ ret = uport->set_rxtrig(uport, bytes);
+ else
+ ret = do_serial8250_set_rxtrig(port, bytes);
+
if (ret < 0)
return ret;
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 1aa07c5187d8..96646d3f2943 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -456,6 +456,8 @@ struct uart_port {
void (*pm)(struct uart_port *, unsigned int state,
unsigned int old);
void (*handle_break)(struct uart_port *);
+ int (*set_rxtrig)(struct uart_port *, unsigned char);
+ int (*get_rxtrig)(struct uart_port *);
int (*rs485_config)(struct uart_port *,
struct ktermios *termios,
struct serial_rs485 *rs485);
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 20/31] serial: 8250: add optional callbacks for rx_trig_bytes
2025-11-30 10:42 ` [PATCH v1 20/31] serial: 8250: add optional callbacks for rx_trig_bytes Crescent Hsieh
@ 2025-12-01 1:58 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 1:58 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> The rx_trig_bytes sysfs attribute adjusts the UART RX FIFO trigger
> level. Some modern 8250 variants require programming device-specific
> registers to change this threshold, which the generic (FCR-based) path
> does not cover.
>
> This patch adds two optional uart_port callbacks:
> - set_rxtrig(port, bytes): program a device-specific RX trigger threshold
> - get_rxtrig(port): read back the current RX trigger threshold
>
> When these callbacks are provided, the 8250 core will use them to
> set/read the hardware-specific threshold. If the callbacks are not
> implemented, the code falls back to the legacy generic path, so existing
> drivers keep their current behavior.
>
> No functional change for drivers that do not implement the new
> callbacks.
...
> - rxtrig_bytes = do_serial8250_get_rxtrig(port);
> + if (uport->get_rxtrig)
> + rxtrig_bytes = uport->get_rxtrig(uport);
> + else
> + rxtrig_bytes = do_serial8250_get_rxtrig(port);
> +
Unneeded blank line.
> if (rxtrig_bytes < 0)
> return rxtrig_bytes;
...
> - ret = do_serial8250_set_rxtrig(port, bytes);
> + if (uport->set_rxtrig)
> + ret = uport->set_rxtrig(uport, bytes);
> + else
> + ret = do_serial8250_set_rxtrig(port, bytes);
> +
Ditto.
> if (ret < 0)
> return ret;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 21/31] serial: 8250_mxpcie: implement rx_trig_bytes callbacks and persist per-port level
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (19 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 20/31] serial: 8250: add optional callbacks for rx_trig_bytes Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:02 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 22/31] serial: 8250_mxupci: " Crescent Hsieh
` (9 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
This patch implements device-specific RX trigger handling for the
rx_trig_bytes sysfs attribute by programming MOXA_PUART_RTL directly.
Changes:
- Add a per-port structure to persist both the registered line and the
RX trigger level, allowing the level to be restored on startup.
- Implement uart_port callbacks:
- set_rxtrig(port, bytes): program MOXA_PUART_RTL and cache the value
- get_rxtrig(port): read back MOXA_PUART_RTL
- Use the cached RX trigger level during startup instead of a fixed
default, while keeping the initial default at 96 for backward
compatibility.
With these callbacks in place, writes to rx_trig_bytes update the
hardware-specific register immediately, and the selected threshold is
preserved across open/close cycles.
No functional change for other 8250 drivers.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 49 +++++++++++++++++++++++----
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 9ba171274221..04b9c9ff5cbf 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -93,11 +93,16 @@
#define MOXA_EVEN_RS_MASK GENMASK(3, 0)
#define MOXA_ODD_RS_MASK GENMASK(7, 4)
+struct mxpcie8250_port {
+ int line;
+ u8 rx_trig_level;
+};
+
struct mxpcie8250 {
struct pci_dev *pdev;
unsigned int supp_rs;
unsigned int num_ports;
- int line[];
+ struct mxpcie8250_port port[];
};
enum {
@@ -243,6 +248,8 @@ static void mxpcie8250_set_termios(struct uart_port *port,
static int mxpcie8250_startup(struct uart_port *port)
{
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
struct uart_8250_port *up = up_to_u8250p(port);
int i, ret;
@@ -255,7 +262,7 @@ static int mxpcie8250_startup(struct uart_port *port)
serial_out(up, MOXA_PUART_SFR, MOXA_PUART_SFR_950);
serial_out(up, MOXA_PUART_TTL, 0);
- serial_out(up, MOXA_PUART_RTL, 96);
+ serial_out(up, MOXA_PUART_RTL, priv->port[port->port_id].rx_trig_level);
serial_out(up, MOXA_PUART_FCL, 16);
serial_out(up, MOXA_PUART_FCH, 110);
@@ -441,6 +448,31 @@ static void mxpcie8250_break_ctl(struct uart_port *port, int break_state)
serial8250_do_break_ctl(port, break_state);
}
+static int mxpcie8250_set_rxtrig(struct uart_port *port, unsigned char bytes)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+
+ if (bytes > 128)
+ return -EINVAL;
+
+ serial_out(up, MOXA_PUART_RTL, bytes);
+ priv->port[port->port_id].rx_trig_level = bytes;
+
+ return 0;
+}
+
+static int mxpcie8250_get_rxtrig(struct uart_port *port)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ int rx_trig_byte;
+
+ rx_trig_byte = serial_in(up, MOXA_PUART_RTL);
+
+ return rx_trig_byte;
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -513,7 +545,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
num_ports = mxpcie8250_get_nports(pdev->device);
- priv = devm_kzalloc(&pdev->dev, struct_size(priv, line, num_ports), GFP_KERNEL);
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, port, num_ports), GFP_KERNEL);
if (!priv)
return -ENOMEM;
@@ -539,6 +571,8 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.unthrottle = mxpcie8250_unthrottle;
up.port.handle_irq = mxpcie8250_handle_irq;
up.port.break_ctl = mxpcie8250_break_ctl;
+ up.port.set_rxtrig = mxpcie8250_set_rxtrig;
+ up.port.get_rxtrig = mxpcie8250_get_rxtrig;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
@@ -547,15 +581,16 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
up.port.iobase, up.port.irq, up.port.iotype);
- priv->line[i] = serial8250_register_8250_port(&up);
+ priv->port[i].line = serial8250_register_8250_port(&up);
- if (priv->line[i] < 0) {
+ if (priv->port[i].line < 0) {
dev_err(&pdev->dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
up.port.iobase, up.port.irq,
- up.port.iotype, priv->line[i]);
+ up.port.iotype, priv->port[i].line);
break;
}
+ priv->port[i].rx_trig_level = 96;
}
pci_set_drvdata(pdev, priv);
@@ -568,7 +603,7 @@ static void mxpcie8250_remove(struct pci_dev *pdev)
unsigned int i;
for (i = 0; i < priv->num_ports; i++)
- serial8250_unregister_port(priv->line[i]);
+ serial8250_unregister_port(priv->port[i].line);
}
static const struct pci_device_id mxpcie8250_pci_ids[] = {
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 21/31] serial: 8250_mxpcie: implement rx_trig_bytes callbacks and persist per-port level
2025-11-30 10:42 ` [PATCH v1 21/31] serial: 8250_mxpcie: implement rx_trig_bytes callbacks and persist per-port level Crescent Hsieh
@ 2025-12-01 2:02 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:02 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> This patch implements device-specific RX trigger handling for the
> rx_trig_bytes sysfs attribute by programming MOXA_PUART_RTL directly.
>
> Changes:
> - Add a per-port structure to persist both the registered line and the
> RX trigger level, allowing the level to be restored on startup.
> - Implement uart_port callbacks:
> - set_rxtrig(port, bytes): program MOXA_PUART_RTL and cache the value
> - get_rxtrig(port): read back MOXA_PUART_RTL
> - Use the cached RX trigger level during startup instead of a fixed
> default, while keeping the initial default at 96 for backward
> compatibility.
>
> With these callbacks in place, writes to rx_trig_bytes update the
> hardware-specific register immediately, and the selected threshold is
> preserved across open/close cycles.
>
> No functional change for other 8250 drivers.
...
> static int mxpcie8250_startup(struct uart_port *port)
> {
> + struct pci_dev *pdev = to_pci_dev(port->dev);
> + struct mxpcie8250 *priv = pci_get_drvdata(pdev);
It's a bit of a detour to simply use dev_get_drvdata() in an agnostic
way. With the above the code will need a change once the device uses
another bus.
> struct uart_8250_port *up = up_to_u8250p(port);
> int i, ret;
> }
...
> +static int mxpcie8250_set_rxtrig(struct uart_port *port, unsigned char bytes)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + struct pci_dev *pdev = to_pci_dev(port->dev);
> + struct mxpcie8250 *priv = pci_get_drvdata(pdev);
Ditto. Aslo locate the lines consistently with the other function
(usually in reversed xmas tree order).
> + if (bytes > 128)
> + return -EINVAL;
> +
> + serial_out(up, MOXA_PUART_RTL, bytes);
> + priv->port[port->port_id].rx_trig_level = bytes;
> +
> + return 0;
> +}
...
> +static int mxpcie8250_get_rxtrig(struct uart_port *port)
> +{
> + struct uart_8250_port *up = up_to_u8250p(port);
> + int rx_trig_byte;
Seems a useless variable. Is there something in the next changes that
justifies its presence?
> + rx_trig_byte = serial_in(up, MOXA_PUART_RTL);
> +
> + return rx_trig_byte;
> +}
...
Also it seems that this change can be split to two:
- preparatory that moves just a line member to a new data structure
- this one which adds required features
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 22/31] serial: 8250_mxupci: implement rx_trig_bytes callbacks and persist per-port level
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (20 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 21/31] serial: 8250_mxpcie: implement rx_trig_bytes callbacks and persist per-port level Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:03 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 23/31] serial: 8250_mxpcie: defer uart_write_wakeup to workqueue Crescent Hsieh
` (8 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Implement device-specific RX trigger handling for the rx_trig_bytes sysfs
attribute on MXUPCI parts by programming the vendor registers directly.
Changes:
- Introduce a per-port structure to persist the registered line and the
RX trigger level, so the level can be restored on startup.
- Implement uart_port callbacks:
- set_rxtrig(port, bytes): program MOXA_UART_RBRTI and cache the level
- get_rxtrig(port): return the cached RX trigger level
- Use the cached RX trigger level during startup instead of a fixed
default, while keeping the initial default at 96 for backward
compatibility.
With these callbacks, writes to rx_trig_bytes update the hardware-specific
register and the selected threshold is preserved across open/close cycles.
No functional change for other 8250 drivers.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 61 ++++++++++++++++++++++++---
1 file changed, 54 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index 0eeaf0fa1538..15565729b7e4 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -86,10 +86,15 @@
#define MOXA_UART_RBRTI 0x06 /* Rx Interrupt Trigger Level */
#define MOXA_UART_THRTL 0x07 /* Tx Interrupt Trigger Level */
+struct mxupci8250_port {
+ int line;
+ u8 rx_trig_level;
+};
+
struct mxupci8250 {
struct pci_dev *pdev;
unsigned int num_ports;
- int line[];
+ struct mxupci8250_port port[];
};
static unsigned short mxupci8250_get_nports(unsigned short device)
@@ -150,6 +155,8 @@ static void mxupci8250_set_termios(struct uart_port *port, struct ktermios *new,
static int mxupci8250_startup(struct uart_port *port)
{
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxupci8250 *priv = pci_get_drvdata(pdev);
struct uart_8250_port *up = up_to_u8250p(port);
int ret;
u8 efr;
@@ -167,7 +174,7 @@ static int mxupci8250_startup(struct uart_port *port)
serial_out(up, UART_EFR, efr);
serial_out(up, MOXA_UART_THRTL, 0);
- serial_out(up, MOXA_UART_RBRTI, 96);
+ serial_out(up, MOXA_UART_RBRTI, priv->port[port->port_id].rx_trig_level);
serial_out(up, MOXA_UART_RBRTL, 32);
serial_out(up, MOXA_UART_RBRTH, 96);
@@ -309,6 +316,43 @@ static int mxupci8250_handle_irq(struct uart_port *port)
return 1;
}
+static int mxupci8250_set_rxtrig(struct uart_port *port, unsigned char bytes)
+{
+ struct uart_8250_port *up = up_to_u8250p(port);
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxupci8250 *priv = pci_get_drvdata(pdev);
+ u8 efr;
+
+ if (bytes > 128)
+ return -EINVAL;
+
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+
+ efr = serial_in(up, UART_EFR);
+ efr |= UART_EFR_ECB;
+ serial_out(up, UART_EFR, efr);
+
+ efr &= ~MOXA_UART_EFR_PAGE_MASK;
+ efr |= MOXA_UART_EFR_PAGE_1;
+ serial_out(up, UART_EFR, efr);
+
+ serial_out(up, MOXA_UART_RBRTI, bytes);
+
+ serial_out(up, UART_LCR, up->lcr);
+
+ priv->port[port->port_id].rx_trig_level = bytes;
+
+ return 0;
+}
+
+static int mxupci8250_get_rxtrig(struct uart_port *port)
+{
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxupci8250 *priv = pci_get_drvdata(pdev);
+
+ return priv->port[port->port_id].rx_trig_level;
+}
+
static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
@@ -324,7 +368,7 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
num_ports = mxupci8250_get_nports(pdev->device);
- priv = devm_kzalloc(&pdev->dev, struct_size(priv, line, num_ports), GFP_KERNEL);
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, port, num_ports), GFP_KERNEL);
if (!priv)
return -ENOMEM;
@@ -346,6 +390,8 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.throttle = mxupci8250_throttle;
up.port.unthrottle = mxupci8250_unthrottle;
up.port.handle_irq = mxupci8250_handle_irq;
+ up.port.set_rxtrig = mxupci8250_set_rxtrig;
+ up.port.get_rxtrig = mxupci8250_get_rxtrig;
for (i = 0; i < num_ports; i++) {
if (serial8250_pci_setup_port(pdev, &up, FL_GET_BASE(FL_BASE2), i * MOXA_UART_OFFSET, 0))
@@ -354,15 +400,16 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
up.port.iobase, up.port.irq, up.port.iotype);
- priv->line[i] = serial8250_register_8250_port(&up);
+ priv->port[i].line = serial8250_register_8250_port(&up);
- if (priv->line[i] < 0) {
+ if (priv->port[i].line < 0) {
dev_err(&pdev->dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
up.port.iobase, up.port.irq,
- up.port.iotype, priv->line[i]);
+ up.port.iotype, priv->port[i].line);
break;
}
+ priv->port[i].rx_trig_level = 96;
}
pci_set_drvdata(pdev, priv);
@@ -375,7 +422,7 @@ static void mxupci8250_remove(struct pci_dev *pdev)
unsigned int i;
for (i = 0; i < priv->num_ports; i++)
- serial8250_unregister_port(priv->line[i]);
+ serial8250_unregister_port(priv->port[i].line);
}
static const struct pci_device_id mxupci8250_pci_ids[] = {
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 22/31] serial: 8250_mxupci: implement rx_trig_bytes callbacks and persist per-port level
2025-11-30 10:42 ` [PATCH v1 22/31] serial: 8250_mxupci: " Crescent Hsieh
@ 2025-12-01 2:03 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:03 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Implement device-specific RX trigger handling for the rx_trig_bytes sysfs
> attribute on MXUPCI parts by programming the vendor registers directly.
>
> Changes:
> - Introduce a per-port structure to persist the registered line and the
> RX trigger level, so the level can be restored on startup.
> - Implement uart_port callbacks:
> - set_rxtrig(port, bytes): program MOXA_UART_RBRTI and cache the level
> - get_rxtrig(port): return the cached RX trigger level
> - Use the cached RX trigger level during startup instead of a fixed
> default, while keeping the initial default at 96 for backward
> compatibility.
>
> With these callbacks, writes to rx_trig_bytes update the hardware-specific
> register and the selected threshold is preserved across open/close cycles.
>
> No functional change for other 8250 drivers.
Same comments applied here as per previous patch.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 23/31] serial: 8250_mxpcie: defer uart_write_wakeup to workqueue
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (21 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 22/31] serial: 8250_mxupci: " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:05 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 24/31] serial: 8250_mxupci: " Crescent Hsieh
` (7 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
When the TX FIFO drops below WAKEUP_CHARS, mxpcie used to call
uart_write_wakeup() directly from the interrupt path. Move this into a
per-port work item so we avoid doing TTY wakeups in interrupt context and
reduce IRQ-side work.
Changes:
- Add per-port state (event_flags, work, cached uport pointer).
- In tx_chars(), set a TXLOW event and schedule the per-port work instead
of calling uart_write_wakeup() directly.
- The work handler test-and-clear the TXLOW bit and calls
uart_write_wakeup().
This keeps IRQ handlers lightweight and avoids potential locking or RT
latency issues while preserving existing behavior.
Note: removal path must cancel pending works before unregistering ports.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 32 +++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 04b9c9ff5cbf..a0deb464a318 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -93,9 +93,14 @@
#define MOXA_EVEN_RS_MASK GENMASK(3, 0)
#define MOXA_ODD_RS_MASK GENMASK(7, 4)
+#define MOXA_EVENT_TXLOW BIT(0)
+
struct mxpcie8250_port {
int line;
+ unsigned long event_flags;
u8 rx_trig_level;
+ struct uart_port *uport;
+ struct work_struct work;
};
struct mxpcie8250 {
@@ -332,6 +337,8 @@ static void mxpcie8250_tx_chars(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
struct tty_port *tport = &port->state->port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
unsigned int count, i;
unsigned char c;
@@ -352,9 +359,10 @@ static void mxpcie8250_tx_chars(struct uart_8250_port *up)
*(port->membase + MOXA_PUART_TX_FIFO_MEM + i) = c;
}
- if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-
+ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) {
+ if (!test_and_set_bit(MOXA_EVENT_TXLOW, &priv->port[port->port_id].event_flags))
+ schedule_work(&priv->port[port->port_id].work);
+ }
if (kfifo_is_empty(&tport->xmit_fifo) && !(up->capabilities & UART_CAP_RPM))
port->ops->stop_tx(port);
}
@@ -473,6 +481,14 @@ static int mxpcie8250_get_rxtrig(struct uart_port *port)
return rx_trig_byte;
}
+static void mxpcie8250_work_handler(struct work_struct *work)
+{
+ struct mxpcie8250_port *priv_port = container_of(work, struct mxpcie8250_port, work);
+
+ if (test_and_clear_bit(MOXA_EVENT_TXLOW, &priv_port->event_flags))
+ uart_write_wakeup(priv_port->uport);
+}
+
static int mxpcie8250_init(struct pci_dev *pdev)
{
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
@@ -533,6 +549,7 @@ static int mxpcie8250_setup(struct pci_dev *pdev,
static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
+ struct uart_8250_port *new_port;
struct mxpcie8250 *priv;
unsigned int i, num_ports;
int ret;
@@ -590,7 +607,12 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.iotype, priv->port[i].line);
break;
}
+ new_port = serial8250_get_port(priv->port[i].line);
+
priv->port[i].rx_trig_level = 96;
+ priv->port[i].uport = &new_port->port;
+
+ INIT_WORK(&priv->port[i].work, mxpcie8250_work_handler);
}
pci_set_drvdata(pdev, priv);
@@ -602,8 +624,10 @@ static void mxpcie8250_remove(struct pci_dev *pdev)
struct mxpcie8250 *priv = pci_get_drvdata(pdev);
unsigned int i;
- for (i = 0; i < priv->num_ports; i++)
+ for (i = 0; i < priv->num_ports; i++) {
+ cancel_work_sync(&priv->port[i].work);
serial8250_unregister_port(priv->port[i].line);
+ }
}
static const struct pci_device_id mxpcie8250_pci_ids[] = {
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 23/31] serial: 8250_mxpcie: defer uart_write_wakeup to workqueue
2025-11-30 10:42 ` [PATCH v1 23/31] serial: 8250_mxpcie: defer uart_write_wakeup to workqueue Crescent Hsieh
@ 2025-12-01 2:05 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:05 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> When the TX FIFO drops below WAKEUP_CHARS, mxpcie used to call
> uart_write_wakeup() directly from the interrupt path. Move this into a
> per-port work item so we avoid doing TTY wakeups in interrupt context and
> reduce IRQ-side work.
>
> Changes:
> - Add per-port state (event_flags, work, cached uport pointer).
> - In tx_chars(), set a TXLOW event and schedule the per-port work instead
> of calling uart_write_wakeup() directly.
> - The work handler test-and-clear the TXLOW bit and calls
> uart_write_wakeup().
>
> This keeps IRQ handlers lightweight and avoids potential locking or RT
> latency issues while preserving existing behavior.
>
> Note: removal path must cancel pending works before unregistering ports.
...
> + struct pci_dev *pdev = to_pci_dev(port->dev);
> + struct mxpcie8250 *priv = pci_get_drvdata(pdev);
dev_get_drvdata();
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 24/31] serial: 8250_mxupci: defer uart_write_wakeup to workqueue
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (22 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 23/31] serial: 8250_mxpcie: defer uart_write_wakeup to workqueue Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:06 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 25/31] serial: 8250_mxpcie: add basic GPIO helper functions Crescent Hsieh
` (6 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
When the TX FIFO drops below WAKEUP_CHARS, mxpcie used to call
uart_write_wakeup() directly from the interrupt path. Move this into a
per-port work item so we avoid doing TTY wakeups in interrupt context and
reduce IRQ-side work.
Changes:
- Add per-port state (event_flags, work, cached uport pointer).
- In tx_chars(), set a TXLOW event and schedule the per-port work instead
of calling uart_write_wakeup() directly.
- The work handler test-and-clear the TXLOW bit and calls
uart_write_wakeup().
This keeps IRQ handlers lightweight and avoids potential locking or RT
latency issues while preserving existing behavior.
Note: removal path must cancel pending works before unregistering ports.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxupci.c | 33 +++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mxupci.c b/drivers/tty/serial/8250/8250_mxupci.c
index 15565729b7e4..a19880b99236 100644
--- a/drivers/tty/serial/8250/8250_mxupci.c
+++ b/drivers/tty/serial/8250/8250_mxupci.c
@@ -86,9 +86,14 @@
#define MOXA_UART_RBRTI 0x06 /* Rx Interrupt Trigger Level */
#define MOXA_UART_THRTL 0x07 /* Tx Interrupt Trigger Level */
+#define MOXA_EVENT_TXLOW BIT(0)
+
struct mxupci8250_port {
int line;
+ unsigned long event_flags;
u8 rx_trig_level;
+ struct uart_port *uport;
+ struct work_struct work;
};
struct mxupci8250 {
@@ -251,6 +256,8 @@ static void mxupci8250_tx_chars(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
struct tty_port *tport = &port->state->port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxupci8250 *priv = pci_get_drvdata(pdev);
unsigned int count, i;
unsigned char c;
@@ -271,9 +278,10 @@ static void mxupci8250_tx_chars(struct uart_8250_port *up)
serial_out(up, UART_TX, c);
}
- if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-
+ if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) {
+ if (!test_and_set_bit(MOXA_EVENT_TXLOW, &priv->port[port->port_id].event_flags))
+ schedule_work(&priv->port[port->port_id].work);
+ }
if (kfifo_is_empty(&tport->xmit_fifo) && !(up->capabilities & UART_CAP_RPM))
port->ops->stop_tx(port);
}
@@ -353,9 +361,19 @@ static int mxupci8250_get_rxtrig(struct uart_port *port)
return priv->port[port->port_id].rx_trig_level;
}
+static void mxupci8250_work_handler(struct work_struct *work)
+{
+ struct mxupci8250_port *priv_port = container_of(work, struct mxupci8250_port, work);
+
+ if (test_and_clear_bit(MOXA_EVENT_TXLOW, &priv_port->event_flags))
+ uart_write_wakeup(priv_port->uport);
+
+}
+
static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port up;
+ struct uart_8250_port *new_port;
struct mxupci8250 *priv;
unsigned int i, num_ports;
int ret;
@@ -409,7 +427,12 @@ static int mxupci8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.iotype, priv->port[i].line);
break;
}
+ new_port = serial8250_get_port(priv->port[i].line);
+
priv->port[i].rx_trig_level = 96;
+ priv->port[i].uport = &new_port->port;
+
+ INIT_WORK(&priv->port[i].work, mxupci8250_work_handler);
}
pci_set_drvdata(pdev, priv);
@@ -421,8 +444,10 @@ static void mxupci8250_remove(struct pci_dev *pdev)
struct mxupci8250 *priv = pci_get_drvdata(pdev);
unsigned int i;
- for (i = 0; i < priv->num_ports; i++)
+ for (i = 0; i < priv->num_ports; i++) {
+ cancel_work_sync(&priv->port[i].work);
serial8250_unregister_port(priv->port[i].line);
+ }
}
static const struct pci_device_id mxupci8250_pci_ids[] = {
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 24/31] serial: 8250_mxupci: defer uart_write_wakeup to workqueue
2025-11-30 10:42 ` [PATCH v1 24/31] serial: 8250_mxupci: " Crescent Hsieh
@ 2025-12-01 2:06 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:06 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> When the TX FIFO drops below WAKEUP_CHARS, mxpcie used to call
> uart_write_wakeup() directly from the interrupt path. Move this into a
> per-port work item so we avoid doing TTY wakeups in interrupt context and
> reduce IRQ-side work.
>
> Changes:
> - Add per-port state (event_flags, work, cached uport pointer).
> - In tx_chars(), set a TXLOW event and schedule the per-port work instead
> of calling uart_write_wakeup() directly.
> - The work handler test-and-clear the TXLOW bit and calls
> uart_write_wakeup().
>
> This keeps IRQ handlers lightweight and avoids potential locking or RT
> latency issues while preserving existing behavior.
>
> Note: removal path must cancel pending works before unregistering ports.
...
> + struct pci_dev *pdev = to_pci_dev(port->dev);
> + struct mxupci8250 *priv = pci_get_drvdata(pdev);
dev_get_drvdata();
...
> +static void mxupci8250_work_handler(struct work_struct *work)
> +{
> + struct mxupci8250_port *priv_port = container_of(work, struct mxupci8250_port, work);
> +
> + if (test_and_clear_bit(MOXA_EVENT_TXLOW, &priv_port->event_flags))
> + uart_write_wakeup(priv_port->uport);
> +
Stray new line.
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 25/31] serial: 8250_mxpcie: add basic GPIO helper functions
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (23 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 24/31] serial: 8250_mxupci: " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:13 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 26/31] serial: 8250_mxpcie: add basic CPLD " Crescent Hsieh
` (5 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Introduce a set of helper functions for accessing the on-board GPIO
registers on Moxa PCIe serial devices. These cover:
- Initializing all pins as outputs
- Setting the direction of individual pins
- Setting or clearing an output pin
- Bulk set/get operations on OUTPUT and DIRECTION registers
These functions do not change any existing behavior yet. They are added
as a preparation step for follow-up patches that will make use of the
GPIOs to control board-specific signals.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 91 +++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index a0deb464a318..6e727b77c105 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -79,11 +79,18 @@
#define MOXA_PUART_RX_FIFO_MEM 0x100 /* Memory Space to Rx FIFO Data Register */
#define MOXA_PUART_TX_FIFO_MEM 0x100 /* Memory Space to Tx FIFO Data Register */
+/* GPIO */
#define MOXA_GPIO_DIRECTION 0x09
#define MOXA_GPIO_OUTPUT 0x0A
#define MOXA_GPIO_PIN2 BIT(2)
+#define MOXA_GPIO_STATE_INPUT 0
+#define MOXA_GPIO_STATE_OUTPUT 1
+
+#define MOXA_GPIO_LOW 0
+#define MOXA_GPIO_HIGH 1
+
#define MOXA_UIR_OFFSET 0x04
#define MOXA_UIR_RS232 0x00
#define MOXA_UIR_RS422 0x01
@@ -120,6 +127,90 @@ static const struct serial_rs485 mxpcie8250_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | SER_RS485_MODE_RS422,
};
+/**
+ * mxpcie8250_gpio_init() - GPIO initialization routine
+ * @iobar_addr: The base address of the GPIO I/O region
+ *
+ * Initializes the GPIO direction. After calling this function, all GPIO
+ * pins will be set to output.
+ */
+static void mxpcie8250_gpio_init(resource_size_t iobar_addr)
+{
+ /* Initialize all the GPIO pins into output state */
+ outb(0xff, iobar_addr + MOXA_GPIO_DIRECTION);
+}
+
+/**
+ * mxpcie8250_gpio_set_direction() - Set GPIO pin direction
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @pin: The target GPIO pin (MOXA_GPIO_PIN0 to MOXA_GPIO_PIN7)
+ * @direction: Desired direction (MOXA_GPIO_STATE_INPUT or MOXA_GPIO_STATE_OUTPUT)
+ *
+ * Sets the direction of the specified GPIO pin. This function should be called
+ * before performing GPIO set or get operations.
+ */
+static void mxpcie8250_gpio_set_direction(resource_size_t iobar_addr, int pin, int direction)
+{
+ u8 cval;
+
+ cval = inb(iobar_addr + MOXA_GPIO_DIRECTION);
+
+ if (direction == MOXA_GPIO_STATE_INPUT)
+ cval &= ~pin;
+ else
+ cval |= pin;
+
+ outb(cval, iobar_addr + MOXA_GPIO_DIRECTION);
+}
+
+/**
+ * mxpcie8250_gpio_set() - Set GPIO output state
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @pin: The target GPIO pin (MOXA_GPIO_PIN0 to MOXA_GPIO_PIN7)
+ * @state: Desired output state (MOXA_GPIO_HIGH or MOXA_GPIO_LOW)
+ *
+ * Sets the output state of the specified GPIO pin.
+ */
+static void mxpcie8250_gpio_set(resource_size_t iobar_addr, int pin, int state)
+{
+ u8 cval;
+
+ cval = inb(iobar_addr + MOXA_GPIO_OUTPUT);
+
+ if (state == MOXA_GPIO_HIGH)
+ cval |= pin;
+ else
+ cval &= ~pin;
+
+ outb(cval, iobar_addr + MOXA_GPIO_OUTPUT);
+}
+
+/**
+ * mxpcie8250_gpio_set_all() - Set all GPIO output/direction pins at once
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @data: The data to set for all pins
+ * @offset: Offset of the GPIO register (MOXA_GPIO_OUTPUT or MOXA_GPIO_DIRECTION)
+ *
+ * Sets the output state or direction of all GPIO pins at once.
+ */
+static void mxpcie8250_gpio_set_all(resource_size_t iobar_addr, u8 data, u8 offset)
+{
+ outb(data, iobar_addr + offset);
+}
+
+/**
+ * mxpcie8250_gpio_get_all() - Get all GPIO input/output pins state at once
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @data: The buffer to store the states of all pins
+ * @offset: Offset of the GPIO register (MOXA_GPIO_INPUT or MOXA_GPIO_OUTPUT)
+ *
+ * Gets the input or output state of all GPIO pins at once.
+ */
+static void mxpcie8250_gpio_get_all(resource_size_t iobar_addr, u8 *data, u8 offset)
+{
+ *data = inb(iobar_addr + offset);
+}
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 25/31] serial: 8250_mxpcie: add basic GPIO helper functions
2025-11-30 10:42 ` [PATCH v1 25/31] serial: 8250_mxpcie: add basic GPIO helper functions Crescent Hsieh
@ 2025-12-01 2:13 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:13 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Introduce a set of helper functions for accessing the on-board GPIO
> registers on Moxa PCIe serial devices. These cover:
>
> - Initializing all pins as outputs
> - Setting the direction of individual pins
> - Setting or clearing an output pin
> - Bulk set/get operations on OUTPUT and DIRECTION registers
> These functions do not change any existing behavior yet. They are added
> as a preparation step for follow-up patches that will make use of the
> GPIOs to control board-specific signals.
Then do not add them. We do not add the code without users. It might
be better for review (or worse ;-) but at the end of the day it needs
to be squashed with the user.
...
> +/**
> + * mxpcie8250_gpio_init() - GPIO initialization routine
> + * @iobar_addr: The base address of the GPIO I/O region
> + *
> + * Initializes the GPIO direction. After calling this function, all GPIO
> + * pins will be set to output.
This is quite dangerous! Why not input? At bare minimum this needs a
good comment to explain why it's not a problem.
> + */
> +static void mxpcie8250_gpio_init(resource_size_t iobar_addr)
> +{
> + /* Initialize all the GPIO pins into output state */
> + outb(0xff, iobar_addr + MOXA_GPIO_DIRECTION);
> +}
...
Why is this not a drivers/gpio/gpio-moxa.c how it's done for Exar, for example?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 26/31] serial: 8250_mxpcie: add basic CPLD helper functions
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (24 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 25/31] serial: 8250_mxpcie: add basic GPIO helper functions Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:25 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 27/31] serial: 8250: Allow dynamic extension of uart_port attr_group Crescent Hsieh
` (4 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Introduce a set of helper functions to access the on-board CPLD on
Moxa PCIe serial devices through the GPIO I/O space. These helpers
cover:
- Initializing the CPLD-related GPIO pins to a safe default state
- Enabling/disabling the CPLD chip select
- Switching between read/write and address/data modes
- Performing single-byte read and write transactions using GPIO
bit-banging, with simple delay and retry logic
These functions do not affect the UART datapath and are not yet used
by the driver. They are added as a preparation step for follow-up
patches that will implement more complex CPLD-based features.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 240 ++++++++++++++++++++++++++
1 file changed, 240 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 6e727b77c105..88ab918fd000 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -6,6 +6,7 @@
* Author: Crescent Hsieh <crescentcy.hsieh@moxa.com>
*/
+#include <linux/delay.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/tty_flip.h>
@@ -80,10 +81,18 @@
#define MOXA_PUART_TX_FIFO_MEM 0x100 /* Memory Space to Tx FIFO Data Register */
/* GPIO */
+#define MOXA_GPIO_INPUT 0x08
#define MOXA_GPIO_DIRECTION 0x09
#define MOXA_GPIO_OUTPUT 0x0A
+#define MOXA_GPIO_PIN0 BIT(0)
+#define MOXA_GPIO_PIN1 BIT(1)
#define MOXA_GPIO_PIN2 BIT(2)
+#define MOXA_GPIO_PIN3 BIT(3)
+#define MOXA_GPIO_PIN4 BIT(4)
+#define MOXA_GPIO_PIN5 BIT(5) /* Address/Data Pin */
+#define MOXA_GPIO_PIN6 BIT(6) /* Read/Write Pin */
+#define MOXA_GPIO_PIN7 BIT(7) /* Chip Select Pin */
#define MOXA_GPIO_STATE_INPUT 0
#define MOXA_GPIO_STATE_OUTPUT 1
@@ -91,6 +100,21 @@
#define MOXA_GPIO_LOW 0
#define MOXA_GPIO_HIGH 1
+/* CPLD */
+#define MOXA_CPLD_RETRY_CNT 5
+
+#define MOXA_CPLD_GET_STATE_BASE 0x10
+#define MOXA_CPLD_SET_STATE_BASE 0x18
+
+#define MOXA_CPLD_DATA_MASK 0x1F /* Pin0 ~ Pin4 */
+#define MOXA_CPLD_CTRL_MASK 0xE0 /* Pin5 ~ Pin7 */
+
+#define MOXA_CPLD_READ 0
+#define MOXA_CPLD_WRITE 1
+
+#define MOXA_CPLD_ADDRESS 0
+#define MOXA_CPLD_DATA 1
+
#define MOXA_UIR_OFFSET 0x04
#define MOXA_UIR_RS232 0x00
#define MOXA_UIR_RS422 0x01
@@ -211,6 +235,218 @@ static void mxpcie8250_gpio_get_all(resource_size_t iobar_addr, u8 *data, u8 off
*data = inb(iobar_addr + offset);
}
+/**
+ * mxpcie8250_cpld_init() - Initialize CPLD control GPIO pins
+ * @iobar_addr: The base address of the GPIO I/O region
+ *
+ * Initialize the GPIO pins used to control the CPLD. Also sets all GPIO pins
+ * to output and drives them HIGH to ensure a safe default state.
+ */
+static void mxpcie8250_cpld_init(resource_size_t iobar_addr)
+{
+ mxpcie8250_gpio_init(iobar_addr);
+
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN7, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN6, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN5, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_HIGH);
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_HIGH);
+}
+
+/**
+ * mxpcie8250_cpld_enable() - Enable the CPLD
+ * @iobar_addr: The base address of the GPIO I/O region
+ *
+ * Enables the CPLD by pulling the chip select pin low.
+ */
+static void mxpcie8250_cpld_enable(resource_size_t iobar_addr)
+{
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN7, MOXA_GPIO_LOW);
+}
+
+/**
+ * mxpcie8250_cpld_disable() - Disable the CPLD and reset all GPIO pins
+ * @iobar_addr: The base address of the GPIO I/O region
+ *
+ * Disables the CPLD by pulling the chip select pin high. Also resets all GPIO
+ * pins to output and drives them HIGH to ensure a safe default state.
+ */
+static void mxpcie8250_cpld_disable(resource_size_t iobar_addr)
+{
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN7, MOXA_GPIO_HIGH);
+
+ /* Set all GPIO pins to output state and pull them HIGH */
+ mxpcie8250_gpio_set_all(iobar_addr, 0xff, MOXA_GPIO_DIRECTION);
+ mxpcie8250_gpio_set_all(iobar_addr, 0xff, MOXA_GPIO_OUTPUT);
+}
+
+/**
+ * mxpcie8250_cpld_set_direction() - Set CPLD read/write direction
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @direction: Desired CPLD direction (MOXA_CPLD_READ or MOXA_CPLD_WRITE)
+ *
+ * Sets the CPLD read/write direction by changing the state of the read/write
+ * control pin.
+ */
+static void mxpcie8250_cpld_set_direction(resource_size_t iobar_addr, int direction)
+{
+ if (direction == MOXA_CPLD_READ)
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN6, MOXA_GPIO_HIGH);
+ else
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN6, MOXA_GPIO_LOW);
+}
+
+/**
+ * mxpcie8250_cpld_set_mode() - Set CPLD address/data mode
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @mode: Desired CPLD mode (MOXA_CPLD_ADDRESS or MOXA_CPLD_DATA)
+ *
+ * Sets the CPLD addr/data mode by changing the state of the address/data
+ * control pin.
+ */
+static void mxpcie8250_cpld_set_mode(resource_size_t iobar_addr, int mode)
+{
+ if (mode == MOXA_CPLD_ADDRESS)
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN5, MOXA_GPIO_LOW);
+ else
+ mxpcie8250_gpio_set(iobar_addr, MOXA_GPIO_PIN5, MOXA_GPIO_HIGH);
+}
+
+/**
+ * mxpcie8250_cpld_read() - Read a byte from the CPLD at a specified address
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @addr: Address in the CPLD to read from
+ * @data: The buffer to store the read value
+ *
+ * Reads a single byte of data from the CPLD at the given address using
+ * GPIO-based communication.
+ */
+static void mxpcie8250_cpld_read(resource_size_t iobar_addr, u8 addr, u8 *data)
+{
+ u8 saved_state, new_state;
+ u8 samples[MOXA_CPLD_RETRY_CNT], votes[MOXA_CPLD_RETRY_CNT];
+ int i, j;
+
+ /* Perform multiple read attempts with majority voting */
+ for (i = 0; i < MOXA_CPLD_RETRY_CNT; i++) {
+ /* Set read/write pin to read state */
+ mxpcie8250_cpld_set_direction(iobar_addr, MOXA_CPLD_READ);
+ /* Set address/data bus pins to output for address phase */
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
+ /* Backup current GPIO output state */
+ mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
+ /* Prepare address to GPIO bus */
+ new_state = saved_state & MOXA_CPLD_CTRL_MASK;
+ new_state |= (addr & MOXA_CPLD_DATA_MASK);
+ /* Output address to GPIO bus */
+ mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
+ /* Switch to address mode (address/data pin) */
+ mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_ADDRESS);
+ /* Enable CPLD by pulling chip select pin low*/
+ mxpcie8250_cpld_enable(iobar_addr);
+ /* Wait for CPLD timing (about 70 ns) */
+ mdelay(1);
+ /* Switch to data mode (address/data pin) */
+ mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_DATA);
+ /* Set address/data bus pins to input for data phase */
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_INPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_INPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_INPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_INPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_INPUT);
+ /* Wait for CPLD timing (about 70 ns) */
+ mdelay(1);
+ /* Read data bus pins */
+ mxpcie8250_gpio_get_all(iobar_addr, data, MOXA_GPIO_INPUT);
+ *data &= MOXA_CPLD_DATA_MASK;
+ /* No need to restore read/write pin (defaults to read); disable CPLD */
+ mxpcie8250_cpld_disable(iobar_addr);
+ /* Store read value for voting */
+ samples[i] = *data;
+ votes[i] = 0;
+
+ for (j = i - 1; j >= 0; j--) {
+ if (samples[j] == samples[i])
+ votes[i]++;
+ }
+ /* Perform majority voting to select stable value */
+ if (votes[i] >= (MOXA_CPLD_RETRY_CNT / 2))
+ break;
+ }
+}
+
+/**
+ * mxpcie8250_cpld_write() - Write a byte to the CPLD at a specified address
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @addr: Address in the CPLD to write to
+ * @data: Data byte to write
+ *
+ * Writes a single byte of data to the CPLD at the given address using
+ * GPIO-based communication. Includes verification with optional retry.
+ */
+static void mxpcie8250_cpld_write(resource_size_t iobar_addr, u8 addr, u8 data)
+{
+ u8 saved_state, new_state, verify_data;
+ int retry_cnt;
+
+ for (retry_cnt = 0; retry_cnt < MOXA_CPLD_RETRY_CNT; retry_cnt++) {
+ /* Set read/write pin to write state */
+ mxpcie8250_cpld_set_direction(iobar_addr, MOXA_CPLD_WRITE);
+ /* Set data bus pins to output for address phase */
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
+ /* Backup current GPIO output state */
+ mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
+ /* Prepare bus value with address bits */
+ new_state = saved_state & MOXA_CPLD_CTRL_MASK;
+ new_state |= (addr & MOXA_CPLD_DATA_MASK);
+ /* Output address to GPIO bus */
+ mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
+ /* Switch to address mode (address/data pin)*/
+ mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_ADDRESS);
+ /* Enable CPLD by pulling chip select pin low */
+ mxpcie8250_cpld_enable(iobar_addr);
+ /* Wait for CPLD timing (about 70 ns) */
+ mdelay(1);
+ /* Set data bus pins to output for data phase */
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
+ mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
+ /* Switch to data mode (address/data pin) */
+ mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_DATA);
+ /* Backup current GPIO output state */
+ mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
+ /* Prepare bus value with data bits */
+ new_state = saved_state & MOXA_CPLD_CTRL_MASK;
+ new_state |= (data & MOXA_CPLD_DATA_MASK);
+ /* Output data to GPIO bus */
+ mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
+ /* Wait for CPLD timing (about 70 ns) */
+ mdelay(1);
+ /* Disable CPLD by releasing chip select pin */
+ mxpcie8250_cpld_disable(iobar_addr);
+
+ if (addr & MOXA_CPLD_SET_STATE_BASE) {
+ mxpcie8250_cpld_read(iobar_addr, ((addr & ~MOXA_CPLD_SET_STATE_BASE) | MOXA_CPLD_GET_STATE_BASE), &verify_data);
+
+ if (verify_data == data)
+ break;
+ }
+ }
+}
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
@@ -585,6 +821,10 @@ static int mxpcie8250_init(struct pci_dev *pdev)
resource_size_t iobar_addr = pci_resource_start(pdev, 2);
u8 cval;
+ mxpcie8250_cpld_init(iobar_addr);
+
+ outb(0x0f, iobar_addr + MOXA_GPIO_DIRECTION);
+
/* Initial terminator */
if (pdev->device == PCI_DEVICE_ID_MOXA_CP114EL ||
pdev->device == PCI_DEVICE_ID_MOXA_CP118EL_A) {
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 26/31] serial: 8250_mxpcie: add basic CPLD helper functions
2025-11-30 10:42 ` [PATCH v1 26/31] serial: 8250_mxpcie: add basic CPLD " Crescent Hsieh
@ 2025-12-01 2:25 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:25 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Introduce a set of helper functions to access the on-board CPLD on
> Moxa PCIe serial devices through the GPIO I/O space. These helpers
> cover:
>
> - Initializing the CPLD-related GPIO pins to a safe default state
> - Enabling/disabling the CPLD chip select
> - Switching between read/write and address/data modes
> - Performing single-byte read and write transactions using GPIO
> bit-banging, with simple delay and retry logic
>
> These functions do not affect the UART datapath and are not yet used
> by the driver. They are added as a preparation step for follow-up
> patches that will implement more complex CPLD-based features.
...
> +static void mxpcie8250_cpld_read(resource_size_t iobar_addr, u8 addr, u8 *data)
> +{
> + u8 saved_state, new_state;
> + u8 samples[MOXA_CPLD_RETRY_CNT], votes[MOXA_CPLD_RETRY_CNT];
> + int i, j;
> +
> + /* Perform multiple read attempts with majority voting */
Why?! Is the HW so buggy?
> + for (i = 0; i < MOXA_CPLD_RETRY_CNT; i++) {
> + /* Set read/write pin to read state */
> + mxpcie8250_cpld_set_direction(iobar_addr, MOXA_CPLD_READ);
> + /* Set address/data bus pins to output for address phase */
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
> + /* Backup current GPIO output state */
> + mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
> + /* Prepare address to GPIO bus */
> + new_state = saved_state & MOXA_CPLD_CTRL_MASK;
> + new_state |= (addr & MOXA_CPLD_DATA_MASK);
> + /* Output address to GPIO bus */
> + mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
> + /* Switch to address mode (address/data pin) */
> + mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_ADDRESS);
> + /* Enable CPLD by pulling chip select pin low*/
MIssed space before */.
> + mxpcie8250_cpld_enable(iobar_addr);
> + /* Wait for CPLD timing (about 70 ns) */
> + mdelay(1);
Why atomic?
And 70ns is more than 10x times less than 1ms!
> + /* Switch to data mode (address/data pin) */
> + mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_DATA);
> + /* Set address/data bus pins to input for data phase */
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_INPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_INPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_INPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_INPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_INPUT);
> + /* Wait for CPLD timing (about 70 ns) */
> + mdelay(1);
Ditto.
> + /* Read data bus pins */
> + mxpcie8250_gpio_get_all(iobar_addr, data, MOXA_GPIO_INPUT);
> + *data &= MOXA_CPLD_DATA_MASK;
> + /* No need to restore read/write pin (defaults to read); disable CPLD */
> + mxpcie8250_cpld_disable(iobar_addr);
> + /* Store read value for voting */
> + samples[i] = *data;
> + votes[i] = 0;
> +
> + for (j = i - 1; j >= 0; j--) {
j = i
while (j--) {
is much easier to understand.
However, the "votes" approach has to be explained "Why?". Bugs in HW?
Other stuff?
> + if (samples[j] == samples[i])
> + votes[i]++;
> + }
> + /* Perform majority voting to select stable value */
> + if (votes[i] >= (MOXA_CPLD_RETRY_CNT / 2))
> + break;
> + }
> +}
> +
> +/**
> + * mxpcie8250_cpld_write() - Write a byte to the CPLD at a specified address
> + * @iobar_addr: The base address of the GPIO I/O region
> + * @addr: Address in the CPLD to write to
> + * @data: Data byte to write
> + *
> + * Writes a single byte of data to the CPLD at the given address using
> + * GPIO-based communication. Includes verification with optional retry.
> + */
> +static void mxpcie8250_cpld_write(resource_size_t iobar_addr, u8 addr, u8 data)
> +{
> + u8 saved_state, new_state, verify_data;
> + int retry_cnt;
> +
> + for (retry_cnt = 0; retry_cnt < MOXA_CPLD_RETRY_CNT; retry_cnt++) {
> + /* Set read/write pin to write state */
> + mxpcie8250_cpld_set_direction(iobar_addr, MOXA_CPLD_WRITE);
> + /* Set data bus pins to output for address phase */
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
This block is repeated at least three times (just with a different
direction), make it a helper and call as many times as you need.
> + /* Backup current GPIO output state */
> + mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
> + /* Prepare bus value with address bits */
> + new_state = saved_state & MOXA_CPLD_CTRL_MASK;
> + new_state |= (addr & MOXA_CPLD_DATA_MASK);
> + /* Output address to GPIO bus */
> + mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
> + /* Switch to address mode (address/data pin)*/
> + mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_ADDRESS);
> + /* Enable CPLD by pulling chip select pin low */
> + mxpcie8250_cpld_enable(iobar_addr);
> + /* Wait for CPLD timing (about 70 ns) */
> + mdelay(1);
See above.
> + /* Set data bus pins to output for data phase */
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN0, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN1, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN2, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN3, MOXA_GPIO_STATE_OUTPUT);
> + mxpcie8250_gpio_set_direction(iobar_addr, MOXA_GPIO_PIN4, MOXA_GPIO_STATE_OUTPUT);
See above.
> + /* Switch to data mode (address/data pin) */
> + mxpcie8250_cpld_set_mode(iobar_addr, MOXA_CPLD_DATA);
> + /* Backup current GPIO output state */
> + mxpcie8250_gpio_get_all(iobar_addr, &saved_state, MOXA_GPIO_OUTPUT);
> + /* Prepare bus value with data bits */
> + new_state = saved_state & MOXA_CPLD_CTRL_MASK;
> + new_state |= (data & MOXA_CPLD_DATA_MASK);
> + /* Output data to GPIO bus */
> + mxpcie8250_gpio_set_all(iobar_addr, new_state, MOXA_GPIO_OUTPUT);
> + /* Wait for CPLD timing (about 70 ns) */
> + mdelay(1);
See above
> + /* Disable CPLD by releasing chip select pin */
> + mxpcie8250_cpld_disable(iobar_addr);
> +
> + if (addr & MOXA_CPLD_SET_STATE_BASE) {
> + mxpcie8250_cpld_read(iobar_addr, ((addr & ~MOXA_CPLD_SET_STATE_BASE) | MOXA_CPLD_GET_STATE_BASE), &verify_data);
> +
> + if (verify_data == data)
> + break;
> + }
> + }
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 27/31] serial: 8250: Allow dynamic extension of uart_port attr_group
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (25 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 26/31] serial: 8250_mxpcie: add basic CPLD " Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:30 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 28/31] serial: 8250_mxpcie: Track current serial interface for later feature gating Crescent Hsieh
` (3 subsequent siblings)
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Currently, uart_port->attr_group can only reference a statically
defined attribute_group, which prevents drivers from appending their
own sysfs attributes.
This enables drivers to inject custom sysfs entries without overriding
the core-provided rxtrig interface.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_core.c | 8 ++++++++
drivers/tty/serial/8250/8250_port.c | 26 ++++++++++++++++++++++++--
include/linux/serial_core.h | 1 +
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 3d8575874759..66b942e9e78a 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -812,6 +812,8 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
uart->port.set_rxtrig = up->port.set_rxtrig;
if (up->port.get_rxtrig)
uart->port.get_rxtrig = up->port.get_rxtrig;
+ if (up->port.attr_group)
+ uart->port.attr_group = up->port.attr_group;
if (up->dl_read)
uart->dl_read = up->dl_read;
if (up->dl_write)
@@ -895,6 +897,12 @@ void serial8250_unregister_port(int line)
uart->port.type = PORT_UNKNOWN;
uart->port.dev = &serial8250_isa_devs->dev;
uart->port.port_id = line;
+
+ if (uart->port.attr_group_allocated) {
+ kfree(uart->port.attr_group->attrs);
+ kfree(uart->port.attr_group);
+ }
+ uart->port.attr_group = NULL;
uart->capabilities = 0;
serial8250_init_port(uart);
serial8250_apply_quirks(uart);
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index d7baceacd4ff..e84879718a51 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -3192,9 +3192,31 @@ static struct attribute_group serial8250_dev_attr_group = {
static void register_dev_spec_attr_grp(struct uart_8250_port *up)
{
const struct serial8250_config *conf_type = &uart_config[up->port.type];
+ struct attribute **upp_attrs = NULL;
+ int upp_attr_num = 0, i;
- if (conf_type->rxtrig_bytes[0])
- up->port.attr_group = &serial8250_dev_attr_group;
+ up->port.attr_group_allocated = false;
+
+ if (up->port.attr_group) {
+ upp_attrs = up->port.attr_group->attrs;
+
+ while (upp_attrs[upp_attr_num])
+ upp_attr_num++;
+
+ up->port.attr_group = kcalloc(1, sizeof(struct attribute_group), GFP_KERNEL);
+ up->port.attr_group->attrs = kcalloc(upp_attr_num + 2, sizeof(struct attribute *), GFP_KERNEL);
+
+ for (i = 0; i < upp_attr_num; ++i)
+ up->port.attr_group->attrs[i] = upp_attrs[i];
+
+ if (conf_type->rxtrig_bytes[0])
+ up->port.attr_group->attrs[upp_attr_num] = &dev_attr_rx_trig_bytes.attr;
+
+ up->port.attr_group_allocated = true;
+ } else {
+ if (conf_type->rxtrig_bytes[0])
+ up->port.attr_group = &serial8250_dev_attr_group;
+ }
}
static void serial8250_config_port(struct uart_port *port, int flags)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 96646d3f2943..95ef7b08b6d8 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -590,6 +590,7 @@ struct uart_port {
unsigned char console_reinit;
const char *name; /* port name */
struct attribute_group *attr_group; /* port specific attributes */
+ bool attr_group_allocated; /* whether attr_group is dynamic allocated */
const struct attribute_group **tty_groups; /* all attributes (serial core use only) */
struct serial_rs485 rs485;
struct serial_rs485 rs485_supported; /* Supported mask for serial_rs485 */
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 27/31] serial: 8250: Allow dynamic extension of uart_port attr_group
2025-11-30 10:42 ` [PATCH v1 27/31] serial: 8250: Allow dynamic extension of uart_port attr_group Crescent Hsieh
@ 2025-12-01 2:30 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:30 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:45 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Currently, uart_port->attr_group can only reference a statically
> defined attribute_group, which prevents drivers from appending their
> own sysfs attributes.
>
> This enables drivers to inject custom sysfs entries without overriding
> the core-provided rxtrig interface.
> + if (up->port.attr_group) {
> + upp_attrs = up->port.attr_group->attrs;
> +
> + while (upp_attrs[upp_attr_num])
> + upp_attr_num++;
> + up->port.attr_group = kcalloc(1, sizeof(struct attribute_group), GFP_KERNEL);
sizeof(*...)
No error check? And why calloc(1)? Shouldn't malloc() be enough?
> + up->port.attr_group->attrs = kcalloc(upp_attr_num + 2, sizeof(struct attribute *), GFP_KERNEL);
sizeof(*)
Error check?
> + for (i = 0; i < upp_attr_num; ++i)
> + up->port.attr_group->attrs[i] = upp_attrs[i];
> +
> + if (conf_type->rxtrig_bytes[0])
> + up->port.attr_group->attrs[upp_attr_num] = &dev_attr_rx_trig_bytes.attr;
> +
> + up->port.attr_group_allocated = true;
> + } else {
> + if (conf_type->rxtrig_bytes[0])
> + up->port.attr_group = &serial8250_dev_attr_group;
> + }
> }
...
> struct uart_port {
> unsigned char console_reinit;
> const char *name; /* port name */
> struct attribute_group *attr_group; /* port specific attributes */
> + bool attr_group_allocated; /* whether attr_group is dynamic allocated */
Is this the best place? Have you run `pahole`?
> const struct attribute_group **tty_groups; /* all attributes (serial core use only) */
> struct serial_rs485 rs485;
> struct serial_rs485 rs485_supported; /* Supported mask for serial_rs485 */
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 28/31] serial: 8250_mxpcie: Track current serial interface for later feature gating
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (26 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 27/31] serial: 8250: Allow dynamic extension of uart_port attr_group Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator Crescent Hsieh
` (2 subsequent siblings)
30 siblings, 0 replies; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Introduce an `interface` field in struct mxpcie8250_port and update it
whenever the serial interface is switched via mxpcie8250_set_interface().
This allows runtime checks based on the active interface (e.g. RS-232 vs
RS-422/485) in later patches, where features such as terminator, pull
state, or auto mode must only be enabled for differential modes.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 88ab918fd000..7a1030a47b00 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -128,6 +128,7 @@
struct mxpcie8250_port {
int line;
+ int interface;
unsigned long event_flags;
u8 rx_trig_level;
struct uart_port *uport;
@@ -505,6 +506,8 @@ static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
}
outb(cval, UIR_addr);
+ priv->port[port_idx].interface = mode;
+
return 0;
}
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (27 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 28/31] serial: 8250_mxpcie: Track current serial interface for later feature gating Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:40 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 30/31] serial: 8250_mxpcie: Add sysfs to control pull state via CPLD Crescent Hsieh
2025-11-30 10:42 ` [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control Crescent Hsieh
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Some Moxa PCIe serial board variants support software-controlled
termination resistors on each port. Users currently have no standardized
interface to enable or disable terminator state from userspace.
This patch introduces the following:
- EXPORT a new sysfs attribute `/sys/class/tty/*/mxpcie8250_terminator`
to allow users to read or set the terminator state (enabled/disabled).
- Implement both CPLD-based and GPIO-based paths depending on board model.
- Track runtime terminator state in `struct mxpcie8250_port`.
- Serialize CPLD modifications using a new `board_lock` spinlock.
Example usage:
# Enable terminator on ttyS*
echo 1 > /sys/class/tty/ttyS*/mxpcie8250_terminator
# Check current state
cat /sys/class/tty/ttyS*/mxpcie8250_terminator
enabled
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 205 ++++++++++++++++++++++++++
1 file changed, 205 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 7a1030a47b00..9dcb91b917a0 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -105,16 +105,22 @@
#define MOXA_CPLD_GET_STATE_BASE 0x10
#define MOXA_CPLD_SET_STATE_BASE 0x18
+#define MOXA_CPLD_STATE_MASK 0x0F
#define MOXA_CPLD_DATA_MASK 0x1F /* Pin0 ~ Pin4 */
#define MOXA_CPLD_CTRL_MASK 0xE0 /* Pin5 ~ Pin7 */
+#define MOXA_CPLD_TERMINATOR_FLAG 0x02
+
#define MOXA_CPLD_READ 0
#define MOXA_CPLD_WRITE 1
#define MOXA_CPLD_ADDRESS 0
#define MOXA_CPLD_DATA 1
+#define MOXA_TERMINATOR_ENABLE 1
+#define MOXA_TERMINATOR_DISABLE 0
+
#define MOXA_UIR_OFFSET 0x04
#define MOXA_UIR_RS232 0x00
#define MOXA_UIR_RS422 0x01
@@ -129,6 +135,7 @@
struct mxpcie8250_port {
int line;
int interface;
+ int terminator;
unsigned long event_flags;
u8 rx_trig_level;
struct uart_port *uport;
@@ -139,6 +146,7 @@ struct mxpcie8250 {
struct pci_dev *pdev;
unsigned int supp_rs;
unsigned int num_ports;
+ spinlock_t board_lock;
struct mxpcie8250_port port[];
};
@@ -448,6 +456,59 @@ static void mxpcie8250_cpld_write(resource_size_t iobar_addr, u8 addr, u8 data)
}
}
+/**
+ * mxpcie8250_cpld_set_terminator() - Set the terminator of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ * @state: Desired terminator state (MOXA_TERMINATOR_ENABLE or MOXA_TERMINATOR_DISABLE)
+ *
+ * Updates the terminator setting in the CPLD for the specified port by reading
+ * the current state, modifying the terminator bit, and writing the updated
+ * state back to the CPLD.
+ */
+static void mxpcie8250_cpld_set_terminator(resource_size_t iobar_addr, u8 port_idx, u8 state)
+{
+ u8 addr, data;
+
+ addr = MOXA_CPLD_GET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_read(iobar_addr, addr, &data);
+
+ data = data & MOXA_CPLD_STATE_MASK;
+
+ if (state == MOXA_TERMINATOR_ENABLE)
+ data |= MOXA_CPLD_TERMINATOR_FLAG;
+ else
+ data &= ~MOXA_CPLD_TERMINATOR_FLAG;
+
+ addr = MOXA_CPLD_SET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_write(iobar_addr, addr, data);
+}
+
+/**
+ * mxpcie8250_cpld_get_terminator() - Get the terminator state of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ *
+ * Reads the terminator from the CPLD by accessing the appropriate GET_STATE
+ * register for the specified port using GPIO-based communication.
+ *
+ * Returns:
+ * MOXA_TERMINATOR_ENABLE if terminator is enabled,
+ * MOXA_TERMINATOR_DISABLE if terminator is disabled.
+ */
+static int mxpcie8250_cpld_get_terminator(resource_size_t iobar_addr, u8 port_idx)
+{
+ u8 addr, data;
+
+ addr = MOXA_CPLD_GET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_read(iobar_addr, addr, &data);
+
+ if (data & MOXA_CPLD_TERMINATOR_FLAG)
+ return MOXA_TERMINATOR_ENABLE;
+
+ return MOXA_TERMINATOR_DISABLE;
+}
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
@@ -487,6 +548,75 @@ static unsigned short mxpcie8250_get_nports(unsigned short device)
return FIELD_GET(0x00F0, device);
}
+static void mxpcie8250_do_set_terminator(struct pci_dev *pdev,
+ unsigned int port_idx,
+ u8 state)
+{
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ u8 cval;
+
+ cval = inb(iobar_addr + MOXA_GPIO_INPUT);
+
+ switch (pdev->device) {
+ case PCI_DEVICE_ID_MOXA_CP132EL:
+ cval &= ~(1 << (port_idx + 2));
+ cval |= (state << (port_idx + 2));
+ break;
+ case PCI_DEVICE_ID_MOXA_CP114EL:
+ case PCI_DEVICE_ID_MOXA_CP118EL_A:
+ cval &= ~(1 << port_idx);
+ cval |= (state << port_idx);
+ break;
+ default:
+ return;
+ }
+ outb(0xff, iobar_addr + MOXA_GPIO_DIRECTION);
+ outb(cval, iobar_addr + MOXA_GPIO_OUTPUT);
+
+ priv->port[port_idx].terminator = state;
+}
+
+static int mxpcie8250_set_terminator(struct uart_port *port,
+ u8 state)
+{
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+
+ if (priv->port[port->port_id].interface == MOXA_UIR_RS232)
+ return -EINVAL;
+
+ switch (pdev->device) {
+ case PCI_DEVICE_ID_MOXA_CP116E_A_A:
+ case PCI_DEVICE_ID_MOXA_CP116E_A_B:
+ case PCI_DEVICE_ID_MOXA_CP118E_A_I:
+ case PCI_DEVICE_ID_MOXA_CP134EL_A:
+ case PCI_DEVICE_ID_MOXA_CP138E_A:
+ spin_lock(&priv->board_lock);
+ mxpcie8250_cpld_set_terminator(iobar_addr, port->port_id, state);
+ spin_unlock(&priv->board_lock);
+ break;
+ /* RS232 only, no need to be set */
+ case PCI_DEVICE_ID_MOXA_CP104EL_A:
+ case PCI_DEVICE_ID_MOXA_CP102E:
+ case PCI_DEVICE_ID_MOXA_CP102EL:
+ case PCI_DEVICE_ID_MOXA_CP168EL_A:
+ /* CP100N series doesn't support SW control terminator */
+ case PCI_DEVICE_ID_MOXA_CP102N:
+ case PCI_DEVICE_ID_MOXA_CP132N:
+ case PCI_DEVICE_ID_MOXA_CP112N:
+ case PCI_DEVICE_ID_MOXA_CP104N:
+ case PCI_DEVICE_ID_MOXA_CP134N:
+ case PCI_DEVICE_ID_MOXA_CP114N:
+ return -ENODEV;
+ default:
+ mxpcie8250_do_set_terminator(pdev, port->port_id, state);
+ }
+
+ return 0;
+}
+
static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
unsigned int port_idx,
u8 mode)
@@ -495,6 +625,9 @@ static int mxpcie8250_set_interface(struct mxpcie8250 *priv,
resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
u8 cval;
+ if (priv->port[port_idx].uport && mode == MOXA_UIR_RS232)
+ mxpcie8250_set_terminator(priv->port[port_idx].uport, MOXA_TERMINATOR_DISABLE);
+
cval = inb(UIR_addr);
if (port_idx % 2) {
@@ -811,6 +944,76 @@ static int mxpcie8250_get_rxtrig(struct uart_port *port)
return rx_trig_byte;
}
+static ssize_t mxpcie8250_terminator_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct tty_port *tport = dev_get_drvdata(dev);
+ struct uart_state *ustate = container_of(tport, struct uart_state, port);
+ struct uart_port *port = ustate->uart_port;
+ int ret;
+ u8 state;
+
+ if (!count)
+ return -EINVAL;
+
+ ret = kstrtou8(buf, 10, &state);
+
+ if (ret < 0)
+ return ret;
+
+ if (state != MOXA_TERMINATOR_ENABLE && state != MOXA_TERMINATOR_DISABLE)
+ return -EINVAL;
+
+ ret = mxpcie8250_set_terminator(port, state);
+
+ if (ret < 0)
+ return ret;
+
+ return count;
+}
+
+static ssize_t mxpcie8250_terminator_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tty_port *tport = dev_get_drvdata(dev);
+ struct uart_state *ustate = container_of(tport, struct uart_state, port);
+ struct uart_port *port = ustate->uart_port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ int ret;
+
+ if (pdev->device == PCI_DEVICE_ID_MOXA_CP118E_A_I ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP138E_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP134EL_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_B) {
+ spin_lock(&priv->board_lock);
+ ret = mxpcie8250_cpld_get_terminator(iobar_addr, port->port_id);
+ spin_unlock(&priv->board_lock);
+ } else {
+ ret = priv->port[port->port_id].terminator;
+ }
+ if (ret == MOXA_TERMINATOR_ENABLE)
+ return sysfs_emit(buf, "enabled\n");
+
+ return sysfs_emit(buf, "disabled\n");
+}
+
+static DEVICE_ATTR_RW(mxpcie8250_terminator);
+
+static struct attribute *mxpcie8250_dev_attrs[] = {
+ &dev_attr_mxpcie8250_terminator.attr,
+ NULL
+};
+
+static struct attribute_group mxpcie8250_dev_attr_group = {
+ .attrs = mxpcie8250_dev_attrs,
+};
+
static void mxpcie8250_work_handler(struct work_struct *work)
{
struct mxpcie8250_port *priv_port = container_of(work, struct mxpcie8250_port, work);
@@ -924,6 +1127,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
up.port.break_ctl = mxpcie8250_break_ctl;
up.port.set_rxtrig = mxpcie8250_set_rxtrig;
up.port.get_rxtrig = mxpcie8250_get_rxtrig;
+ up.port.attr_group = &mxpcie8250_dev_attr_group;
for (i = 0; i < num_ports; i++) {
if (mxpcie8250_setup(pdev, priv, &up, i))
@@ -943,6 +1147,7 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id
}
new_port = serial8250_get_port(priv->port[i].line);
+ priv->port[i].terminator = MOXA_TERMINATOR_DISABLE;
priv->port[i].rx_trig_level = 96;
priv->port[i].uport = &new_port->port;
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator
2025-11-30 10:42 ` [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator Crescent Hsieh
@ 2025-12-01 2:40 ` Andy Shevchenko
2025-12-03 2:54 ` Crescent Hsieh
0 siblings, 1 reply; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:40 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Some Moxa PCIe serial board variants support software-controlled
> termination resistors on each port. Users currently have no standardized
> interface to enable or disable terminator state from userspace.
>
> This patch introduces the following:
>
> - EXPORT a new sysfs attribute `/sys/class/tty/*/mxpcie8250_terminator`
> to allow users to read or set the terminator state (enabled/disabled).
> - Implement both CPLD-based and GPIO-based paths depending on board model.
> - Track runtime terminator state in `struct mxpcie8250_port`.
> - Serialize CPLD modifications using a new `board_lock` spinlock.
>
> Example usage:
>
> # Enable terminator on ttyS*
> echo 1 > /sys/class/tty/ttyS*/mxpcie8250_terminator
>
> # Check current state
> cat /sys/class/tty/ttyS*/mxpcie8250_terminator
> enabled
This introduces an ABI without documentation update. It's no go.
...
> +#define MOXA_CPLD_STATE_MASK 0x0F
>
> #define MOXA_CPLD_DATA_MASK 0x1F /* Pin0 ~ Pin4 */
> #define MOXA_CPLD_CTRL_MASK 0xE0 /* Pin5 ~ Pin7 */
Use GENMASK() for the above.
...
> struct mxpcie8250_port {
Run `pahole`.
> int line;
> int interface;
> + int terminator;
> unsigned long event_flags;
> u8 rx_trig_level;
> struct uart_port *uport;
> struct mxpcie8250 {
> struct pci_dev *pdev;
> unsigned int supp_rs;
> unsigned int num_ports;
> + spinlock_t board_lock;
> struct mxpcie8250_port port[];
> };
...
> +/**
> + * mxpcie8250_cpld_get_terminator() - Get the terminator state of the specified port
> + * @iobar_addr: The base address of the GPIO I/O region
> + * @port_idx: The port index (0 to 7)
> + *
> + * Reads the terminator from the CPLD by accessing the appropriate GET_STATE
> + * register for the specified port using GPIO-based communication.
> + *
> + * Returns:
> + * MOXA_TERMINATOR_ENABLE if terminator is enabled,
> + * MOXA_TERMINATOR_DISABLE if terminator is disabled.
Have you rendered this with the kernel-doc script? I believe you want
a list, so you need something like
* * List item 1
* * List item 2
> + */
...
> +static void mxpcie8250_do_set_terminator(struct pci_dev *pdev,
> + unsigned int port_idx,
> + u8 state)
> +{
> + struct mxpcie8250 *priv = pci_get_drvdata(pdev);
> + resource_size_t iobar_addr = pci_resource_start(pdev, 2);
> + u8 cval;
> +
> + cval = inb(iobar_addr + MOXA_GPIO_INPUT);
> +
> + switch (pdev->device) {
> + case PCI_DEVICE_ID_MOXA_CP132EL:
> + cval &= ~(1 << (port_idx + 2));
BIT()
> + cval |= (state << (port_idx + 2));
state can be more than one bit set, is it a problem?
> + break;
> + case PCI_DEVICE_ID_MOXA_CP114EL:
> + case PCI_DEVICE_ID_MOXA_CP118EL_A:
> + cval &= ~(1 << port_idx);
> + cval |= (state << port_idx);
Same questions as above.
> + break;
> + default:
> + return;
> + }
> + outb(0xff, iobar_addr + MOXA_GPIO_DIRECTION);
> + outb(cval, iobar_addr + MOXA_GPIO_OUTPUT);
> +
> + priv->port[port_idx].terminator = state;
> +}
...
> +static int mxpcie8250_set_terminator(struct uart_port *port,
> + u8 state)
> +{
> + struct pci_dev *pdev = to_pci_dev(port->dev);
> + struct mxpcie8250 *priv = pci_get_drvdata(pdev);
> + resource_size_t iobar_addr = pci_resource_start(pdev, 2);
Why can't you use what is stored in the "port"? IIRC there are 3
variables: 2 for MMIO (membase/mapbase) and one for IO (iobase).
> + if (priv->port[port->port_id].interface == MOXA_UIR_RS232)
> + return -EINVAL;
> +
> + switch (pdev->device) {
> + case PCI_DEVICE_ID_MOXA_CP116E_A_A:
> + case PCI_DEVICE_ID_MOXA_CP116E_A_B:
> + case PCI_DEVICE_ID_MOXA_CP118E_A_I:
> + case PCI_DEVICE_ID_MOXA_CP134EL_A:
> + case PCI_DEVICE_ID_MOXA_CP138E_A:
> + spin_lock(&priv->board_lock);
> + mxpcie8250_cpld_set_terminator(iobar_addr, port->port_id, state);
> + spin_unlock(&priv->board_lock);
> + break;
> + /* RS232 only, no need to be set */
> + case PCI_DEVICE_ID_MOXA_CP104EL_A:
> + case PCI_DEVICE_ID_MOXA_CP102E:
> + case PCI_DEVICE_ID_MOXA_CP102EL:
> + case PCI_DEVICE_ID_MOXA_CP168EL_A:
> + /* CP100N series doesn't support SW control terminator */
> + case PCI_DEVICE_ID_MOXA_CP102N:
> + case PCI_DEVICE_ID_MOXA_CP132N:
> + case PCI_DEVICE_ID_MOXA_CP112N:
> + case PCI_DEVICE_ID_MOXA_CP104N:
> + case PCI_DEVICE_ID_MOXA_CP134N:
> + case PCI_DEVICE_ID_MOXA_CP114N:
> + return -ENODEV;
> + default:
> + mxpcie8250_do_set_terminator(pdev, port->port_id, state);
Missing break, but see below.
> + }
> +
> + return 0;
Just move it to each case (group of cases) where it's needed.
> +}
...
> +static ssize_t mxpcie8250_terminator_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + struct tty_port *tport = dev_get_drvdata(dev);
> + struct uart_state *ustate = container_of(tport, struct uart_state, port);
> + struct uart_port *port = ustate->uart_port;
> + int ret;
> + u8 state;
> + if (!count)
> + return -EINVAL;
Dead code?
> + ret = kstrtou8(buf, 10, &state);
Why is this strictly decimal?
> +
Unneeded blank line.
> + if (ret < 0)
> + return ret;
> + if (state != MOXA_TERMINATOR_ENABLE && state != MOXA_TERMINATOR_DISABLE)
> + return -EINVAL;
> +
> + ret = mxpcie8250_set_terminator(port, state);
> +
Ditto.
> + if (ret < 0)
> + return ret;
> +
> + return count;
> +}
...
> + spin_lock(&priv->board_lock);
> + ret = mxpcie8250_cpld_get_terminator(iobar_addr, port->port_id);
> + spin_unlock(&priv->board_lock);
scoped_guard() from cleanup.h helps here.
...
> + if (ret == MOXA_TERMINATOR_ENABLE)
> + return sysfs_emit(buf, "enabled\n");
> +
> + return sysfs_emit(buf, "disabled\n");
str_enabled_disabled() from string_choices.h helps here.
> +}
> +
Unneeded blank line.
> +static DEVICE_ATTR_RW(mxpcie8250_terminator);
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator
2025-12-01 2:40 ` Andy Shevchenko
@ 2025-12-03 2:54 ` Crescent Hsieh
2025-12-03 9:21 ` Andy Shevchenko
0 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-12-03 2:54 UTC (permalink / raw)
To: Andy Shevchenko
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Mon, Dec 01, 2025 at 04:40:51AM +0200, Andy Shevchenko wrote:
> On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> <crescentcy.hsieh@moxa.com> wrote:
> >
> > Some Moxa PCIe serial board variants support software-controlled
> > termination resistors on each port. Users currently have no standardized
> > interface to enable or disable terminator state from userspace.
> >
> > This patch introduces the following:
> >
> > - EXPORT a new sysfs attribute `/sys/class/tty/*/mxpcie8250_terminator`
> > to allow users to read or set the terminator state (enabled/disabled).
> > - Implement both CPLD-based and GPIO-based paths depending on board model.
> > - Track runtime terminator state in `struct mxpcie8250_port`.
> > - Serialize CPLD modifications using a new `board_lock` spinlock.
> >
> > Example usage:
> >
> > # Enable terminator on ttyS*
> > echo 1 > /sys/class/tty/ttyS*/mxpcie8250_terminator
> >
> > # Check current state
> > cat /sys/class/tty/ttyS*/mxpcie8250_terminator
> > enabled
>
> This introduces an ABI without documentation update. It's no go.
Just to confirm my understanding — for any new user-visible ABI such
as a sysfs attribute, the corresponding documentation under
Documentation/ABI/ must be included in the same patch/series?
---
Sincerely,
Crescent Hsieh
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator
2025-12-03 2:54 ` Crescent Hsieh
@ 2025-12-03 9:21 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-03 9:21 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Wed, Dec 3, 2025 at 4:55 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> On Mon, Dec 01, 2025 at 04:40:51AM +0200, Andy Shevchenko wrote:
> > On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> > <crescentcy.hsieh@moxa.com> wrote:
...
> > > Example usage:
> > >
> > > # Enable terminator on ttyS*
> > > echo 1 > /sys/class/tty/ttyS*/mxpcie8250_terminator
> > >
> > > # Check current state
> > > cat /sys/class/tty/ttyS*/mxpcie8250_terminator
> > > enabled
> >
> > This introduces an ABI without documentation update. It's no go.
>
> Just to confirm my understanding — for any new user-visible ABI such
> as a sysfs attribute, the corresponding documentation under
> Documentation/ABI/ must be included in the same patch/series?
Yes.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 30/31] serial: 8250_mxpcie: Add sysfs to control pull state via CPLD
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (28 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 29/31] serial: 8250_mxpcie: Add sysfs to control terminator Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:42 ` Andy Shevchenko
2025-11-30 10:42 ` [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control Crescent Hsieh
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Some Moxa PCIe boards provide a CPLD-controlled pull/bias state.
Expose a per-port sysfs attribute to read and set the pull state from
userspace.
This patch:
- Defines MOXA_CPLD_PULL_STATE_FLAG and {ENABLE,DISABLE} values.
- Implements mxpcie8250_cpld_{set,get}_pull_state() with board_lock
to serialize CPLD access.
- Exports "mxpcie8250_pull_state" in the driver's attr group.
- Restricts support to CPLD-based models (CP118E-A-I, CP138E-A,
CP134EL-A, CP116E-A-A, CP116E-A-B); return -ENODEV on others.
Example:
# Enable pull state on ttyS*
echo 1 > /sys/class/tty/ttyS*/mxpcie8250_pull_state
# Query pull state
cat /sys/class/tty/ttyS*/mxpcie8250_pull_state
enabled
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 133 ++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index 9dcb91b917a0..e9e3d03b7712 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -110,6 +110,7 @@
#define MOXA_CPLD_DATA_MASK 0x1F /* Pin0 ~ Pin4 */
#define MOXA_CPLD_CTRL_MASK 0xE0 /* Pin5 ~ Pin7 */
+#define MOXA_CPLD_PULL_STATE_FLAG 0x01
#define MOXA_CPLD_TERMINATOR_FLAG 0x02
#define MOXA_CPLD_READ 0
@@ -121,6 +122,9 @@
#define MOXA_TERMINATOR_ENABLE 1
#define MOXA_TERMINATOR_DISABLE 0
+#define MOXA_PULL_STATE_ENABLE 1
+#define MOXA_PULL_STATE_DISABLE 0
+
#define MOXA_UIR_OFFSET 0x04
#define MOXA_UIR_RS232 0x00
#define MOXA_UIR_RS422 0x01
@@ -509,6 +513,59 @@ static int mxpcie8250_cpld_get_terminator(resource_size_t iobar_addr, u8 port_id
return MOXA_TERMINATOR_DISABLE;
}
+/**
+ * mxpcie8250_cpld_set_pull_state() - Set the pull state of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ * @state: Desired pull state (MOXA_PULL_STATE_ENABLE or MOXA_PULL_STATE_DISABLE)
+ *
+ * Updates the pull state setting in the CPLD for the specified port by reading
+ * the current state, modifying the pull state bit, and writing the updated
+ * state back to the CPLD.
+ */
+static void mxpcie8250_cpld_set_pull_state(resource_size_t iobar_addr, u8 port_idx, u8 state)
+{
+ u8 addr, data;
+
+ addr = MOXA_CPLD_GET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_read(iobar_addr, addr, &data);
+
+ data = data & MOXA_CPLD_STATE_MASK;
+
+ if (state == MOXA_PULL_STATE_ENABLE)
+ data |= MOXA_CPLD_PULL_STATE_FLAG;
+ else
+ data &= ~MOXA_CPLD_PULL_STATE_FLAG;
+
+ addr = MOXA_CPLD_SET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_write(iobar_addr, addr, data);
+}
+
+/**
+ * mxpcie8250_cpld_get_pull_state() - Get the pull state of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ *
+ * Reads the pull state from the CPLD by accessing the appropriate GET_STATE
+ * register for the specified port using GPIO-based communication.
+ *
+ * Returns:
+ * MOXA_PULL_STATE_ENABLE if pull state is enabled,
+ * MOXA_PULL_STATE_DISABLE if pull state is disabled.
+ */
+static int mxpcie8250_cpld_get_pull_state(resource_size_t iobar_addr, u8 port_idx)
+{
+ u8 addr, data;
+
+ addr = MOXA_CPLD_GET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_read(iobar_addr, addr, &data);
+
+ if (data & MOXA_CPLD_PULL_STATE_FLAG)
+ return MOXA_PULL_STATE_ENABLE;
+
+ return MOXA_PULL_STATE_DISABLE;
+}
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
@@ -1003,10 +1060,86 @@ static ssize_t mxpcie8250_terminator_show(struct device *dev,
return sysfs_emit(buf, "disabled\n");
}
+static ssize_t mxpcie8250_pull_state_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct tty_port *tport = dev_get_drvdata(dev);
+ struct uart_state *ustate = container_of(tport, struct uart_state, port);
+ struct uart_port *port = ustate->uart_port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ int ret;
+ u8 state;
+
+ if (!count)
+ return -EINVAL;
+
+ ret = kstrtou8(buf, 10, &state);
+
+ if (ret < 0)
+ return ret;
+
+ if (state != MOXA_PULL_STATE_ENABLE && state != MOXA_PULL_STATE_DISABLE)
+ return -EINVAL;
+
+ if (priv->port[port->port_id].interface == MOXA_UIR_RS232) {
+ dev_warn(dev, "The serial interface of this port cannot be RS232\n");
+ return -EINVAL;
+ }
+ if (pdev->device == PCI_DEVICE_ID_MOXA_CP118E_A_I ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP138E_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP134EL_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_B) {
+ spin_lock(&priv->board_lock);
+ mxpcie8250_cpld_set_pull_state(iobar_addr, port->port_id, state);
+ spin_unlock(&priv->board_lock);
+
+ return count;
+ }
+
+ return -ENODEV;
+}
+
+static ssize_t mxpcie8250_pull_state_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct tty_port *tport = dev_get_drvdata(dev);
+ struct uart_state *ustate = container_of(tport, struct uart_state, port);
+ struct uart_port *port = ustate->uart_port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ int ret;
+
+ if (pdev->device == PCI_DEVICE_ID_MOXA_CP118E_A_I ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP138E_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP134EL_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_B) {
+ spin_lock(&priv->board_lock);
+ ret = mxpcie8250_cpld_get_pull_state(iobar_addr, port->port_id);
+ spin_unlock(&priv->board_lock);
+
+ if (ret == MOXA_PULL_STATE_ENABLE)
+ return sysfs_emit(buf, "enabled\n");
+
+ return sysfs_emit(buf, "disabled\n");
+ }
+
+ return -ENODEV;
+}
+
static DEVICE_ATTR_RW(mxpcie8250_terminator);
+static DEVICE_ATTR_RW(mxpcie8250_pull_state);
static struct attribute *mxpcie8250_dev_attrs[] = {
&dev_attr_mxpcie8250_terminator.attr,
+ &dev_attr_mxpcie8250_pull_state.attr,
NULL
};
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 30/31] serial: 8250_mxpcie: Add sysfs to control pull state via CPLD
2025-11-30 10:42 ` [PATCH v1 30/31] serial: 8250_mxpcie: Add sysfs to control pull state via CPLD Crescent Hsieh
@ 2025-12-01 2:42 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:42 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Some Moxa PCIe boards provide a CPLD-controlled pull/bias state.
> Expose a per-port sysfs attribute to read and set the pull state from
> userspace.
>
> This patch:
> - Defines MOXA_CPLD_PULL_STATE_FLAG and {ENABLE,DISABLE} values.
> - Implements mxpcie8250_cpld_{set,get}_pull_state() with board_lock
> to serialize CPLD access.
> - Exports "mxpcie8250_pull_state" in the driver's attr group.
> - Restricts support to CPLD-based models (CP118E-A-I, CP138E-A,
> CP134EL-A, CP116E-A-A, CP116E-A-B); return -ENODEV on others.
>
> Example:
> # Enable pull state on ttyS*
> echo 1 > /sys/class/tty/ttyS*/mxpcie8250_pull_state
>
> # Query pull state
> cat /sys/class/tty/ttyS*/mxpcie8250_pull_state
> enabled
Okay, this all reminds me of the pin control subsystem. It has already
established an interface to do things, why do we need this custom one
here?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-11-30 10:41 [PATCH v1 00/31] serial: 8250: consolidate Moxa UPCI/PCIe support under 8250 drivers Crescent Hsieh
` (29 preceding siblings ...)
2025-11-30 10:42 ` [PATCH v1 30/31] serial: 8250_mxpcie: Add sysfs to control pull state via CPLD Crescent Hsieh
@ 2025-11-30 10:42 ` Crescent Hsieh
2025-12-01 2:45 ` Andy Shevchenko
30 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-11-30 10:42 UTC (permalink / raw)
To: gregkh, jirislaby, ilpo.jarvinen, andy.shevchenko
Cc: linux-kernel, linux-serial, crescentcy.hsieh
Moxa CP118E/CP138E/CP134EL/CP116E boards support a hardware "auto mode"
in RS485-2W where the CPLD can automatically configure terminator and
pull-state based on the selected baud rate and line condition. This mode
is not meant to be kept enabled continuously — instead, it is triggered
for a short period (about 2s) to let the hardware calibrate itself.
This patch adds a write-only sysfs attribute that requests a one-shot
hardware auto-adjust of terminator and pull-state. Writing a supported
baud rate value (one of 9600, 19200, 38400, 57600, 115200, 230400,
460800, or 921600) into the attribute programs the CPLD baud code and
runs a temporary AUTO mode cycle (about 2s) on RS485-2W ports of the
supported boards. Invalid interfaces or devices are rejected.
Signed-off-by: Crescent Hsieh <crescentcy.hsieh@moxa.com>
---
drivers/tty/serial/8250/8250_mxpcie.c | 143 ++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index e9e3d03b7712..b3146cac0298 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c
@@ -107,11 +107,15 @@
#define MOXA_CPLD_SET_STATE_BASE 0x18
#define MOXA_CPLD_STATE_MASK 0x0F
+#define MOXA_CPLD_SET_BAUD_BASE 0x08
+#define MOXA_CPLD_BAUD_MASK 0x07
+
#define MOXA_CPLD_DATA_MASK 0x1F /* Pin0 ~ Pin4 */
#define MOXA_CPLD_CTRL_MASK 0xE0 /* Pin5 ~ Pin7 */
#define MOXA_CPLD_PULL_STATE_FLAG 0x01
#define MOXA_CPLD_TERMINATOR_FLAG 0x02
+#define MOXA_CPLD_AUTO_MODE_FLAG 0x08
#define MOXA_CPLD_READ 0
#define MOXA_CPLD_WRITE 1
@@ -125,6 +129,18 @@
#define MOXA_PULL_STATE_ENABLE 1
#define MOXA_PULL_STATE_DISABLE 0
+#define MOXA_AUTO_MODE_ENABLE 1
+#define MOXA_AUTO_MODE_DISABLE 0
+
+#define MOXA_CPLD_BAUD_9600 0
+#define MOXA_CPLD_BAUD_19200 1
+#define MOXA_CPLD_BAUD_38400 2
+#define MOXA_CPLD_BAUD_57600 3
+#define MOXA_CPLD_BAUD_115200 4
+#define MOXA_CPLD_BAUD_230400 5
+#define MOXA_CPLD_BAUD_460800 6
+#define MOXA_CPLD_BAUD_921600 7
+
#define MOXA_UIR_OFFSET 0x04
#define MOXA_UIR_RS232 0x00
#define MOXA_UIR_RS422 0x01
@@ -566,6 +582,54 @@ static int mxpcie8250_cpld_get_pull_state(resource_size_t iobar_addr, u8 port_id
return MOXA_PULL_STATE_DISABLE;
}
+/**
+ * mxpcie8250_cpld_set_auto_mode() - Set the auto mode of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ * @state: Desired auto mode state (MOXA_AUTO_MODE_ENABLE or MOXA_AUTO_MODE_DISABLE)
+ *
+ * Updates the auto mode setting in the CPLD for the specified port by reading
+ * the current state, modifying the auto mode bit, and writing the updated
+ * state back to the CPLD.
+ */
+static void mxpcie8250_cpld_set_auto_mode(resource_size_t iobar_addr, u8 port_idx, u8 state)
+{
+ u8 addr, data;
+
+ addr = MOXA_CPLD_GET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_read(iobar_addr, addr, &data);
+
+ data = data & MOXA_CPLD_STATE_MASK;
+
+ if (state == MOXA_AUTO_MODE_ENABLE)
+ data |= MOXA_CPLD_AUTO_MODE_FLAG;
+ else
+ data &= ~MOXA_CPLD_AUTO_MODE_FLAG;
+
+ addr = MOXA_CPLD_SET_STATE_BASE + port_idx;
+ mxpcie8250_cpld_write(iobar_addr, addr, data);
+}
+
+/**
+ * mxpcie8250_cpld_set_baud_rate() - Set the baud rate code of the specified port
+ * @iobar_addr: The base address of the GPIO I/O region
+ * @port_idx: The port index (0 to 7)
+ * @baud: CPLD baud rate code (MOXA_CPLD_BAUD_9600 ... MOXA_CPLD_BAUD_921600)
+ *
+ * Writes the baud rate selection value directly into the CPLD SET_BAUD register
+ * for the specified port. The caller must ensure the value is pre-mapped to
+ * the 3-bit CPLD baud code.
+ */
+static void mxpcie8250_cpld_set_baud_rate(resource_size_t iobar_addr, u8 port_idx, u8 baud)
+{
+ u8 addr, data;
+
+ data = baud & MOXA_CPLD_BAUD_MASK;
+
+ addr = MOXA_CPLD_SET_BAUD_BASE + port_idx;
+ mxpcie8250_cpld_write(iobar_addr, addr, data);
+}
+
static bool mxpcie8250_is_mini_pcie(unsigned short device)
{
if (device == PCI_DEVICE_ID_MOXA_CP102N ||
@@ -1134,12 +1198,91 @@ static ssize_t mxpcie8250_pull_state_show(struct device *dev,
return -ENODEV;
}
+static ssize_t mxpcie8250_auto_mode_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct tty_port *tport = dev_get_drvdata(dev);
+ struct uart_state *ustate = container_of(tport, struct uart_state, port);
+ struct uart_port *port = ustate->uart_port;
+ struct pci_dev *pdev = to_pci_dev(port->dev);
+ struct mxpcie8250 *priv = pci_get_drvdata(pdev);
+ resource_size_t iobar_addr = pci_resource_start(pdev, 2);
+ int ret;
+ u32 baud;
+
+ if (!count)
+ return -EINVAL;
+
+ ret = kstrtou32(buf, 10, &baud);
+
+ if (ret < 0)
+ return ret;
+
+ if (priv->port[port->port_id].interface != MOXA_UIR_RS485_2W) {
+ dev_warn(dev, "The serial interface of this port should be RS485-2W\n");
+ return -EINVAL;
+ }
+ if (pdev->device == PCI_DEVICE_ID_MOXA_CP118E_A_I ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP138E_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP134EL_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_A ||
+ pdev->device == PCI_DEVICE_ID_MOXA_CP116E_A_B) {
+ switch (baud) {
+ case 9600:
+ baud = MOXA_CPLD_BAUD_9600;
+ break;
+ case 19200:
+ baud = MOXA_CPLD_BAUD_19200;
+ break;
+ case 38400:
+ baud = MOXA_CPLD_BAUD_38400;
+ break;
+ case 57600:
+ baud = MOXA_CPLD_BAUD_57600;
+ break;
+ case 115200:
+ baud = MOXA_CPLD_BAUD_115200;
+ break;
+ case 230400:
+ baud = MOXA_CPLD_BAUD_230400;
+ break;
+ case 460800:
+ baud = MOXA_CPLD_BAUD_460800;
+ break;
+ case 921600:
+ baud = MOXA_CPLD_BAUD_921600;
+ break;
+ default:
+ dev_warn(dev, "The baud rate should be one of 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600\n");
+ return -EINVAL;
+ }
+ spin_lock(&priv->board_lock);
+ mxpcie8250_cpld_set_baud_rate(iobar_addr, port->port_id, baud);
+ mxpcie8250_cpld_set_auto_mode(iobar_addr, port->port_id, MOXA_AUTO_MODE_ENABLE);
+ spin_unlock(&priv->board_lock);
+
+ msleep(2000);
+
+ spin_lock(&priv->board_lock);
+ mxpcie8250_cpld_set_auto_mode(iobar_addr, port->port_id, MOXA_AUTO_MODE_DISABLE);
+ spin_unlock(&priv->board_lock);
+
+ return count;
+ }
+
+ return -ENODEV;
+}
+
static DEVICE_ATTR_RW(mxpcie8250_terminator);
static DEVICE_ATTR_RW(mxpcie8250_pull_state);
+static DEVICE_ATTR_WO(mxpcie8250_auto_mode);
static struct attribute *mxpcie8250_dev_attrs[] = {
&dev_attr_mxpcie8250_terminator.attr,
&dev_attr_mxpcie8250_pull_state.attr,
+ &dev_attr_mxpcie8250_auto_mode.attr,
NULL
};
--
2.45.2
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-11-30 10:42 ` [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control Crescent Hsieh
@ 2025-12-01 2:45 ` Andy Shevchenko
2025-12-03 2:55 ` Crescent Hsieh
0 siblings, 1 reply; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-01 2:45 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
<crescentcy.hsieh@moxa.com> wrote:
>
> Moxa CP118E/CP138E/CP134EL/CP116E boards support a hardware "auto mode"
> in RS485-2W where the CPLD can automatically configure terminator and
> pull-state based on the selected baud rate and line condition. This mode
> is not meant to be kept enabled continuously — instead, it is triggered
> for a short period (about 2s) to let the hardware calibrate itself.
>
> This patch adds a write-only sysfs attribute that requests a one-shot
> hardware auto-adjust of terminator and pull-state. Writing a supported
> baud rate value (one of 9600, 19200, 38400, 57600, 115200, 230400,
> 460800, or 921600) into the attribute programs the CPLD baud code and
> runs a temporary AUTO mode cycle (about 2s) on RS485-2W ports of the
> supported boards. Invalid interfaces or devices are rejected.
I'm not going to review this, the patch series is already quite big. I
suggest you to start from the small things in a different series E.g.,
the first series is just converting MOXA from custom to 8250-based
(assuming all features are kept working while ABI is being broken,
which has to be explained in the commit message(s) / cover letter of
that series), the second one is about splitting 8250_pci to the other
Moxa case. When this is done, we may go forward with the additional
features.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-12-01 2:45 ` Andy Shevchenko
@ 2025-12-03 2:55 ` Crescent Hsieh
2025-12-03 9:24 ` Andy Shevchenko
0 siblings, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-12-03 2:55 UTC (permalink / raw)
To: Andy Shevchenko
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Mon, Dec 01, 2025 at 04:45:58AM +0200, Andy Shevchenko wrote:
> On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> <crescentcy.hsieh@moxa.com> wrote:
> >
> > Moxa CP118E/CP138E/CP134EL/CP116E boards support a hardware "auto mode"
> > in RS485-2W where the CPLD can automatically configure terminator and
> > pull-state based on the selected baud rate and line condition. This mode
> > is not meant to be kept enabled continuously — instead, it is triggered
> > for a short period (about 2s) to let the hardware calibrate itself.
> >
> > This patch adds a write-only sysfs attribute that requests a one-shot
> > hardware auto-adjust of terminator and pull-state. Writing a supported
> > baud rate value (one of 9600, 19200, 38400, 57600, 115200, 230400,
> > 460800, or 921600) into the attribute programs the CPLD baud code and
> > runs a temporary AUTO mode cycle (about 2s) on RS485-2W ports of the
> > supported boards. Invalid interfaces or devices are rejected.
>
> I'm not going to review this, the patch series is already quite big. I
> suggest you to start from the small things in a different series E.g.,
> the first series is just converting MOXA from custom to 8250-based
> (assuming all features are kept working while ABI is being broken,
> which has to be explained in the commit message(s) / cover letter of
> that series), the second one is about splitting 8250_pci to the other
> Moxa case. When this is done, we may go forward with the additional
> features.
Hi Andy,
Thanks a lot for spending so much time reviewing this large patch set.
I appreciate the detailed feedback.
I will split this big patch series into smaller and more focused series
to make it easier to review.
Thanks again for your guidance.
Sincerely,
Crescent Hsieh
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-12-03 2:55 ` Crescent Hsieh
@ 2025-12-03 9:24 ` Andy Shevchenko
2025-12-03 9:28 ` Andy Shevchenko
2025-12-05 5:26 ` Crescent Hsieh
0 siblings, 2 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-03 9:24 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Wed, Dec 3, 2025 at 4:56 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> On Mon, Dec 01, 2025 at 04:45:58AM +0200, Andy Shevchenko wrote:
> > On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> > <crescentcy.hsieh@moxa.com> wrote:
...
> > I'm not going to review this, the patch series is already quite big. I
> > suggest you to start from the small things in a different series E.g.,
> > the first series is just converting MOXA from custom to 8250-based
> > (assuming all features are kept working while ABI is being broken,
In case you are wondering what I was talking about in the above, I
meant move from /dev/ttyMIxx to /dev/ttySxx. This will break all the
current kernel command lines and hence setups with the explicit
mention of the /dev/ttyMIxx, such as console=. There might be other
breakages, but I leave it up to you to research and come up with a
solution.
> > which has to be explained in the commit message(s) / cover letter of
> > that series), the second one is about splitting 8250_pci to the other
> > Moxa case. When this is done, we may go forward with the additional
> > features.
> Thanks a lot for spending so much time reviewing this large patch set.
> I appreciate the detailed feedback.
You're welcome!
> I will split this big patch series into smaller and more focused series
> to make it easier to review.
>
> Thanks again for your guidance.
Any time!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-12-03 9:24 ` Andy Shevchenko
@ 2025-12-03 9:28 ` Andy Shevchenko
2025-12-05 5:26 ` Crescent Hsieh
1 sibling, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-03 9:28 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Wed, Dec 3, 2025 at 11:24 AM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Wed, Dec 3, 2025 at 4:56 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> > On Mon, Dec 01, 2025 at 04:45:58AM +0200, Andy Shevchenko wrote:
> > > On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> > > <crescentcy.hsieh@moxa.com> wrote:
...
> > > while ABI is being broken,
>
> In case you are wondering what I was talking about in the above, I
> meant move from /dev/ttyMIxx to /dev/ttySxx. This will break all the
> current kernel command lines and hence setups with the explicit
> mention of the /dev/ttyMIxx, such as console=.
FWIW, we used to have in the past more than one case like this, so if
it's well justified and customers are aware of the change, it may go
in.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-12-03 9:24 ` Andy Shevchenko
2025-12-03 9:28 ` Andy Shevchenko
@ 2025-12-05 5:26 ` Crescent Hsieh
2025-12-05 8:35 ` Andy Shevchenko
1 sibling, 1 reply; 68+ messages in thread
From: Crescent Hsieh @ 2025-12-05 5:26 UTC (permalink / raw)
To: Andy Shevchenko
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Wed, Dec 03, 2025 at 11:24:58AM +0200, Andy Shevchenko wrote:
> On Wed, Dec 3, 2025 at 4:56 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> > On Mon, Dec 01, 2025 at 04:45:58AM +0200, Andy Shevchenko wrote:
> > > On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> > > <crescentcy.hsieh@moxa.com> wrote:
>
> ...
>
> > > I'm not going to review this, the patch series is already quite big. I
> > > suggest you to start from the small things in a different series E.g.,
> > > the first series is just converting MOXA from custom to 8250-based
> > > (assuming all features are kept working while ABI is being broken,
>
> In case you are wondering what I was talking about in the above, I
> meant move from /dev/ttyMIxx to /dev/ttySxx. This will break all the
> current kernel command lines and hence setups with the explicit
> mention of the /dev/ttyMIxx, such as console=. There might be other
> breakages, but I leave it up to you to research and come up with a
> solution.
Just to clarify my intention: the in-tree UPCI serial driver (mxser) has
been unmaintained for years, and my goal is to replace it with a clean
8250-based implementation that preserves reasonable user expectations
while following the upstream serial framework. This will require some
analysis to reconcile the legacy behavior with what upstream expects.
I’d also like to ask about patch ordering. Since the PCIe serial driver
is much simpler to migrate and has minimal user impact, would it be
acceptable to upstream the PCIe conversion first, before the more
complex UPCI transition? I’m happy to follow whichever order makes
review easiest for you.
---
Sincerely,
Crescent Hsieh
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [PATCH v1 31/31] serial: 8250_mxpcie: add RS485-2W auto-adjust sysfs control
2025-12-05 5:26 ` Crescent Hsieh
@ 2025-12-05 8:35 ` Andy Shevchenko
0 siblings, 0 replies; 68+ messages in thread
From: Andy Shevchenko @ 2025-12-05 8:35 UTC (permalink / raw)
To: Crescent Hsieh
Cc: gregkh, jirislaby, ilpo.jarvinen, linux-kernel, linux-serial
On Fri, Dec 5, 2025 at 7:26 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> On Wed, Dec 03, 2025 at 11:24:58AM +0200, Andy Shevchenko wrote:
> > On Wed, Dec 3, 2025 at 4:56 AM Crescent Hsieh <crescentcy.hsieh@moxa.com> wrote:
> > > On Mon, Dec 01, 2025 at 04:45:58AM +0200, Andy Shevchenko wrote:
> > > > On Sun, Nov 30, 2025 at 12:46 PM Crescent Hsieh
> > > > <crescentcy.hsieh@moxa.com> wrote:
...
> > > > I'm not going to review this, the patch series is already quite big. I
> > > > suggest you to start from the small things in a different series E.g.,
> > > > the first series is just converting MOXA from custom to 8250-based
> > > > (assuming all features are kept working while ABI is being broken,
> >
> > In case you are wondering what I was talking about in the above, I
> > meant move from /dev/ttyMIxx to /dev/ttySxx. This will break all the
> > current kernel command lines and hence setups with the explicit
> > mention of the /dev/ttyMIxx, such as console=. There might be other
> > breakages, but I leave it up to you to research and come up with a
> > solution.
>
> Just to clarify my intention: the in-tree UPCI serial driver (mxser) has
> been unmaintained for years, and my goal is to replace it with a clean
> 8250-based implementation that preserves reasonable user expectations
> while following the upstream serial framework. This will require some
> analysis to reconcile the legacy behavior with what upstream expects.
Right, so it's a good justification to break the above on the
expectations that the users most likely don't use the in-kernel driver
as it's unmaintained and has received no bug fixes, etc.
> I’d also like to ask about patch ordering. Since the PCIe serial driver
> is much simpler to migrate and has minimal user impact, would it be
> acceptable to upstream the PCIe conversion first, before the more
> complex UPCI transition? I’m happy to follow whichever order makes
> review easiest for you.
I don't see the downsides of this order. I believe the order of these
big parts is not so important per se.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 68+ messages in thread