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From: Linu Cherian <linu.cherian@arm.com>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Will Deacon <will@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Marc Zyngier <maz@kernel.org>, Dev Jain <dev.jain@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 13/13] arm64: mm: Provide level hint for flush_tlb_page()
Date: Wed, 7 Jan 2026 20:14:38 +0530	[thread overview]
Message-ID: <aV5xVhE1sf4l0gRf@a079125.arm.com> (raw)
In-Reply-To: <20251216144601.2106412-14-ryan.roberts@arm.com>



On Tue, Dec 16, 2025 at 02:45:58PM +0000, Ryan Roberts wrote:
> Previously tlb invalidations issued by __flush_tlb_page() did not
> contain a level hint. But the function is clearly only ever targeting
> level 3 tlb entries and its documentation agrees:
> 
>   | this operation only invalidates a single, last-level page-table
>   | entry and therefore does not affect any walk-caches
> 
> However, it turns out that the function was actually being used to
> invalidate a level 2 mapping via flush_tlb_fix_spurious_fault_pmd(). The
> bug was benign because the level hint was not set so the HW would still
> invalidate the PMD mapping, and also because the TLBF_NONOTIFY flag was
> set, the bounds of the mapping were never used for anything else.
> 
> Now that we have the new and improved range-invalidation API, it is
> trival to fix flush_tlb_fix_spurious_fault_pmd() to explicitly flush the
> whole range (locally, without notification and last level only). So
> let's do that, and then update __flush_tlb_page() to hint level 3.
> 
> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
> ---
>  arch/arm64/include/asm/pgtable.h  | 5 +++--
>  arch/arm64/include/asm/tlbflush.h | 2 +-
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b96a7ca465a1..61f57647361a 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -138,8 +138,9 @@ static inline void arch_leave_lazy_mmu_mode(void)
>  #define flush_tlb_fix_spurious_fault(vma, address, ptep)	\
>  	__flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
>  
> -#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)	\
> -	__flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
> +#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)			\
> +	__flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2,	\
> +			  TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE)
>  
>  /*
>   * ZERO_PAGE is a global shared page that is always zero: used
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index fa5aee990742..f24211b51df3 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -577,7 +577,7 @@ static inline void __flush_tlb_page(struct vm_area_struct *vma,
>  	unsigned long start = round_down(uaddr, PAGE_SIZE);
>  	unsigned long end = start + PAGE_SIZE;
>  
> -	___flush_tlb_range(vma, start, end, PAGE_SIZE, TLBI_TTL_UNKNOWN,
> +	___flush_tlb_range(vma, start, end, PAGE_SIZE, 3,
>  			   TLBF_NOWALKCACHE | flags);
>  }


Reviewed-by: Linu Cherian <linu.cherian@arm.com>


      reply	other threads:[~2026-01-07 14:44 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-16 14:45 [PATCH v1 00/13] arm64: Refactor TLB invalidation API and implementation Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 01/13] arm64: mm: Re-implement the __tlbi_level macro as a C function Ryan Roberts
2025-12-16 17:53   ` Jonathan Cameron
2026-01-02 14:18     ` Ryan Roberts
2026-01-05  5:30   ` Linu Cherian
2026-01-05 17:09     ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 02/13] arm64: mm: Introduce a C wrapper for by-range TLB invalidation Ryan Roberts
2026-01-05  5:33   ` Linu Cherian
2026-01-05 17:12     ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 03/13] arm64: mm: Implicitly invalidate user ASID based on TLBI operation Ryan Roberts
2025-12-16 18:01   ` Jonathan Cameron
2026-01-02 14:20     ` Ryan Roberts
2025-12-18  6:30   ` Linu Cherian
2025-12-18  7:05     ` Linu Cherian
2025-12-18 15:47       ` Linu Cherian
2026-01-02 14:30         ` Ryan Roberts
2026-01-05 13:03           ` Linu Cherian
2026-01-05  5:34   ` Linu Cherian
2026-01-05 17:13     ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Ryan Roberts
2026-01-05  5:35   ` Linu Cherian
2025-12-16 14:45 ` [PATCH v1 05/13] arm64: mm: Inline __TLBI_VADDR_RANGE() into __tlbi_range() Ryan Roberts
2026-01-05  5:35   ` Linu Cherian
2025-12-16 14:45 ` [PATCH v1 06/13] arm64: mm: Re-implement the __flush_tlb_range_op macro in C Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 07/13] arm64: mm: Simplify __TLBI_RANGE_NUM() macro Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 08/13] arm64: mm: Simplify __flush_tlb_range_limit_excess() Ryan Roberts
2025-12-17  8:12   ` Dev Jain
2026-01-02 15:23     ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 09/13] arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid() Ryan Roberts
2026-01-06  3:25   ` Linu Cherian
2025-12-16 14:45 ` [PATCH v1 10/13] arm64: mm: Refactor __flush_tlb_range() to take flags Ryan Roberts
2026-01-06  4:51   ` Linu Cherian
2025-12-16 14:45 ` [PATCH v1 11/13] arm64: mm: More flags for __flush_tlb_range() Ryan Roberts
2026-01-06 15:28   ` Linu Cherian
2026-01-12 11:52     ` Ryan Roberts
2026-01-07  3:21   ` Linu Cherian
2026-01-12 12:00     ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 12/13] arm64: mm: Wrap flush_tlb_page() around ___flush_tlb_range() Ryan Roberts
2026-01-07  9:57   ` Linu Cherian
2025-12-16 14:45 ` [PATCH v1 13/13] arm64: mm: Provide level hint for flush_tlb_page() Ryan Roberts
2026-01-07 14:44   ` Linu Cherian [this message]

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