* [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx @ 2024-10-28 1:13 Inochi Amaoto 2024-10-28 13:09 ` Andrew Lunn 0 siblings, 1 reply; 10+ messages in thread From: Inochi Amaoto @ 2024-10-28 1:13 UTC (permalink / raw) To: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille Cc: Liu Gui, Yixun Lan, Longbin Li, Inochi Amaoto, devicetree, linux-riscv, linux-kernel, netdev Add DT configuration for ethernet controller for cv18xx SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> --- .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 4 ++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 49 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts index 26b57e15adc1..a0acae675a82 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -55,6 +55,10 @@ &emmc { non-removable; }; +&gmac0 { + status = "okay"; +}; + &sdhci0 { status = "okay"; bus-width = <4>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index c18822ec849f..50933e5b4c75 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { status = "disabled"; }; + gmac0: ethernet@4070000 { + compatible = "snps,dwmac-3.70a"; + reg = <0x04070000 0x10000>; + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; + clock-names = "stmmaceth", "ptp_ref"; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + phy-handle = <&phy0>; + phy-mode = "rmii"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <1>; + }; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; -- 2.47.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-28 1:13 [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx Inochi Amaoto @ 2024-10-28 13:09 ` Andrew Lunn 2024-10-28 22:43 ` Inochi Amaoto 0 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2024-10-28 13:09 UTC (permalink / raw) To: Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > status = "disabled"; > }; > > + gmac0: ethernet@4070000 { > + compatible = "snps,dwmac-3.70a"; > + reg = <0x04070000 0x10000>; > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > + clock-names = "stmmaceth", "ptp_ref"; > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + phy-handle = <&phy0>; > + phy-mode = "rmii"; > + rx-fifo-depth = <8192>; > + tx-fifo-depth = <8192>; > + snps,multicast-filter-bins = <0>; > + snps,perfect-filter-entries = <1>; > + snps,aal; > + snps,txpbl = <8>; > + snps,rxpbl = <8>; > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > + status = "disabled"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + phy0: phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + }; > + }; It is not clear to me what cv18xx.dtsi represents, and where the PHY node should be, here, or in a .dts file. Is this a SOM, and the PHY is on the SOM? Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-28 13:09 ` Andrew Lunn @ 2024-10-28 22:43 ` Inochi Amaoto 2024-10-29 2:50 ` Andrew Lunn 2024-10-31 6:18 ` Inochi Amaoto 0 siblings, 2 replies; 10+ messages in thread From: Inochi Amaoto @ 2024-10-28 22:43 UTC (permalink / raw) To: Andrew Lunn, Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote: > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > > status = "disabled"; > > }; > > > > + gmac0: ethernet@4070000 { > > + compatible = "snps,dwmac-3.70a"; > > + reg = <0x04070000 0x10000>; > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > + clock-names = "stmmaceth", "ptp_ref"; > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "macirq"; > > + phy-handle = <&phy0>; > > + phy-mode = "rmii"; > > + rx-fifo-depth = <8192>; > > + tx-fifo-depth = <8192>; > > + snps,multicast-filter-bins = <0>; > > + snps,perfect-filter-entries = <1>; > > + snps,aal; > > + snps,txpbl = <8>; > > + snps,rxpbl = <8>; > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > + status = "disabled"; > > + > > + mdio { > > + compatible = "snps,dwmac-mdio"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + phy0: phy@0 { > > + compatible = "ethernet-phy-ieee802.3-c22"; > > + reg = <0>; > > + }; > > + }; > > It is not clear to me what cv18xx.dtsi represents, This is a include file to define common ip for the whole cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > and where the PHY node should be, here, or in a .dts file. > Is this a SOM, and the PHY is on the SOM? The phy is on the SoC, it is embedded, and no external phy is supported. So I think the phy node should stay here, not in the dts file. Regards, Inochi ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-28 22:43 ` Inochi Amaoto @ 2024-10-29 2:50 ` Andrew Lunn 2024-10-29 3:36 ` Inochi Amaoto 2024-10-31 6:18 ` Inochi Amaoto 1 sibling, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2024-10-29 2:50 UTC (permalink / raw) To: Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Tue, Oct 29, 2024 at 06:43:03AM +0800, Inochi Amaoto wrote: > On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote: > > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > > > status = "disabled"; > > > }; > > > > > > + gmac0: ethernet@4070000 { > > > + compatible = "snps,dwmac-3.70a"; > > > + reg = <0x04070000 0x10000>; > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > + clock-names = "stmmaceth", "ptp_ref"; > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "macirq"; > > > + phy-handle = <&phy0>; > > > + phy-mode = "rmii"; > > > + rx-fifo-depth = <8192>; > > > + tx-fifo-depth = <8192>; > > > + snps,multicast-filter-bins = <0>; > > > + snps,perfect-filter-entries = <1>; > > > + snps,aal; > > > + snps,txpbl = <8>; > > > + snps,rxpbl = <8>; > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > + status = "disabled"; > > > + > > > + mdio { > > > + compatible = "snps,dwmac-mdio"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + phy0: phy@0 { > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > + reg = <0>; > > > + }; > > > + }; > > > > It is not clear to me what cv18xx.dtsi represents, > > This is a include file to define common ip for the whole > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > and where the PHY node should be, here, or in a .dts file. > > Is this a SOM, and the PHY is on the SOM? > > The phy is on the SoC, it is embedded, and no external phy > is supported. So I think the phy node should stay here, not > in the dts file. So this is correct when the PHY is internal. However, this is normally expressed by setting phy-mode to "internal". The stmmac driver might however not allow that? If not, please put a comment indicating the PHY is part of the SoC. Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-29 2:50 ` Andrew Lunn @ 2024-10-29 3:36 ` Inochi Amaoto 0 siblings, 0 replies; 10+ messages in thread From: Inochi Amaoto @ 2024-10-29 3:36 UTC (permalink / raw) To: Andrew Lunn, Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Tue, Oct 29, 2024 at 03:50:41AM +0100, Andrew Lunn wrote: > On Tue, Oct 29, 2024 at 06:43:03AM +0800, Inochi Amaoto wrote: > > On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote: > > > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > > > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > > > > status = "disabled"; > > > > }; > > > > > > > > + gmac0: ethernet@4070000 { > > > > + compatible = "snps,dwmac-3.70a"; > > > > + reg = <0x04070000 0x10000>; > > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > > + clock-names = "stmmaceth", "ptp_ref"; > > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "macirq"; > > > > + phy-handle = <&phy0>; > > > > + phy-mode = "rmii"; > > > > + rx-fifo-depth = <8192>; > > > > + tx-fifo-depth = <8192>; > > > > + snps,multicast-filter-bins = <0>; > > > > + snps,perfect-filter-entries = <1>; > > > > + snps,aal; > > > > + snps,txpbl = <8>; > > > > + snps,rxpbl = <8>; > > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > > + status = "disabled"; > > > > + > > > > + mdio { > > > > + compatible = "snps,dwmac-mdio"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + phy0: phy@0 { > > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > > + reg = <0>; > > > > + }; > > > > + }; > > > > > > It is not clear to me what cv18xx.dtsi represents, > > > > This is a include file to define common ip for the whole > > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > > > and where the PHY node should be, here, or in a .dts file. > > > Is this a SOM, and the PHY is on the SOM? > > > > The phy is on the SoC, it is embedded, and no external phy > > is supported. So I think the phy node should stay here, not > > in the dts file. > > So this is correct when the PHY is internal. However, this is normally > expressed by setting phy-mode to "internal". The stmmac driver might > however not allow that? If not, please put a comment indicating the > PHY is part of the SoC. > > Andrew Thanks, I will try "internal" and check whether it is OK, and add a comment if not. Regards, Inochi ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-28 22:43 ` Inochi Amaoto 2024-10-29 2:50 ` Andrew Lunn @ 2024-10-31 6:18 ` Inochi Amaoto 2024-10-31 13:04 ` Andrew Lunn 1 sibling, 1 reply; 10+ messages in thread From: Inochi Amaoto @ 2024-10-31 6:18 UTC (permalink / raw) To: Andrew Lunn, Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Tue, Oct 29, 2024 at 06:43:03AM +0800, Inochi Amaoto wrote: > On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote: > > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > > > status = "disabled"; > > > }; > > > > > > + gmac0: ethernet@4070000 { > > > + compatible = "snps,dwmac-3.70a"; > > > + reg = <0x04070000 0x10000>; > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > + clock-names = "stmmaceth", "ptp_ref"; > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "macirq"; > > > + phy-handle = <&phy0>; > > > + phy-mode = "rmii"; > > > + rx-fifo-depth = <8192>; > > > + tx-fifo-depth = <8192>; > > > + snps,multicast-filter-bins = <0>; > > > + snps,perfect-filter-entries = <1>; > > > + snps,aal; > > > + snps,txpbl = <8>; > > > + snps,rxpbl = <8>; > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > + status = "disabled"; > > > + > > > + mdio { > > > + compatible = "snps,dwmac-mdio"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + phy0: phy@0 { > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > + reg = <0>; > > > + }; > > > + }; > > > > It is not clear to me what cv18xx.dtsi represents, > > This is a include file to define common ip for the whole > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > and where the PHY node should be, here, or in a .dts file. > > Is this a SOM, and the PHY is on the SOM? > > The phy is on the SoC, it is embedded, and no external phy > is supported. So I think the phy node should stay here, not > in the dts file. There is a mistake, Some package supports external rmii/mii phy. So I will move this phy definition to board specific. Regards, Inochi ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-31 6:18 ` Inochi Amaoto @ 2024-10-31 13:04 ` Andrew Lunn 2024-10-31 22:46 ` Inochi Amaoto 0 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2024-10-31 13:04 UTC (permalink / raw) To: Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev > > > > + gmac0: ethernet@4070000 { > > > > + compatible = "snps,dwmac-3.70a"; > > > > + reg = <0x04070000 0x10000>; > > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > > + clock-names = "stmmaceth", "ptp_ref"; > > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "macirq"; > > > > + phy-handle = <&phy0>; > > > > + phy-mode = "rmii"; > > > > + rx-fifo-depth = <8192>; > > > > + tx-fifo-depth = <8192>; > > > > + snps,multicast-filter-bins = <0>; > > > > + snps,perfect-filter-entries = <1>; > > > > + snps,aal; > > > > + snps,txpbl = <8>; > > > > + snps,rxpbl = <8>; > > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > > + status = "disabled"; > > > > + > > > > + mdio { > > > > + compatible = "snps,dwmac-mdio"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + phy0: phy@0 { > > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > > + reg = <0>; > > > > + }; > > > > + }; > > > > > > It is not clear to me what cv18xx.dtsi represents, > > > > This is a include file to define common ip for the whole > > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > > > and where the PHY node should be, here, or in a .dts file. > > > Is this a SOM, and the PHY is on the SOM? > > > > The phy is on the SoC, it is embedded, and no external phy > > is supported. So I think the phy node should stay here, not > > in the dts file. > > There is a mistake, Some package supports external rmii/mii > phy. So I will move this phy definition to board specific. When there is an external PHY, does the internal PHY still exists? If it does, it should be listed, even if it is not used. Do the internal and external PHY share the same MDIO bus? I've seen some SoCs with complex MDIO muxes for internal vs external PHYs. Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-31 13:04 ` Andrew Lunn @ 2024-10-31 22:46 ` Inochi Amaoto 2024-11-01 12:40 ` Andrew Lunn 0 siblings, 1 reply; 10+ messages in thread From: Inochi Amaoto @ 2024-10-31 22:46 UTC (permalink / raw) To: Andrew Lunn, Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Thu, Oct 31, 2024 at 02:04:31PM +0100, Andrew Lunn wrote: > > > > > + gmac0: ethernet@4070000 { > > > > > + compatible = "snps,dwmac-3.70a"; > > > > > + reg = <0x04070000 0x10000>; > > > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > > > + clock-names = "stmmaceth", "ptp_ref"; > > > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > > > + interrupt-names = "macirq"; > > > > > + phy-handle = <&phy0>; > > > > > + phy-mode = "rmii"; > > > > > + rx-fifo-depth = <8192>; > > > > > + tx-fifo-depth = <8192>; > > > > > + snps,multicast-filter-bins = <0>; > > > > > + snps,perfect-filter-entries = <1>; > > > > > + snps,aal; > > > > > + snps,txpbl = <8>; > > > > > + snps,rxpbl = <8>; > > > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > > > + status = "disabled"; > > > > > + > > > > > + mdio { > > > > > + compatible = "snps,dwmac-mdio"; > > > > > + #address-cells = <1>; > > > > > + #size-cells = <0>; > > > > > + > > > > > + phy0: phy@0 { > > > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > > > + reg = <0>; > > > > > + }; > > > > > + }; > > > > > > > > It is not clear to me what cv18xx.dtsi represents, > > > > > > This is a include file to define common ip for the whole > > > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > > > > > and where the PHY node should be, here, or in a .dts file. > > > > Is this a SOM, and the PHY is on the SOM? > > > > > > The phy is on the SoC, it is embedded, and no external phy > > > is supported. So I think the phy node should stay here, not > > > in the dts file. > > > > There is a mistake, Some package supports external rmii/mii > > phy. So I will move this phy definition to board specific. > > When there is an external PHY, does the internal PHY still exists? If > it does, it should be listed, even if it is not used. > > Do the internal and external PHY share the same MDIO bus? They share the same MDIO bus and phy id setting. When an external phy is select, the internal one is not initialized and can not be accessed by the SoC. > I've seen some SoCs with complex MDIO muxes for internal vs external > PHYs. > > Andrew There is a switch register on the SoC to decide which phy/mode is used. By defaut is internal one with rmii mode. I think a driver is needed to handle this properly. Regards, Inochi ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-10-31 22:46 ` Inochi Amaoto @ 2024-11-01 12:40 ` Andrew Lunn 2024-11-02 0:49 ` Inochi Amaoto 0 siblings, 1 reply; 10+ messages in thread From: Andrew Lunn @ 2024-11-01 12:40 UTC (permalink / raw) To: Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev > > > > > > + mdio { > > > > > > + compatible = "snps,dwmac-mdio"; > > > > > > + #address-cells = <1>; > > > > > > + #size-cells = <0>; > > > > > > + > > > > > > + phy0: phy@0 { > > > > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > > > > + reg = <0>; > > > > > > + }; > > > > > > + }; > > > > > > > > > > It is not clear to me what cv18xx.dtsi represents, > > > > > > > > This is a include file to define common ip for the whole > > > > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > > > > > > > and where the PHY node should be, here, or in a .dts file. > > > > > Is this a SOM, and the PHY is on the SOM? > > > > > > > > The phy is on the SoC, it is embedded, and no external phy > > > > is supported. So I think the phy node should stay here, not > > > > in the dts file. > > > > > > There is a mistake, Some package supports external rmii/mii > > > phy. So I will move this phy definition to board specific. > > > > When there is an external PHY, does the internal PHY still exists? If > > it does, it should be listed, even if it is not used. > > > > Do the internal and external PHY share the same MDIO bus? > > They share the same MDIO bus and phy id setting. What do you mean by phy ID? > When an external phy > is select, the internal one is not initialized and can not be accessed > by the SoC. > > > I've seen some SoCs with complex MDIO muxes for internal vs external > > PHYs. > > > > Andrew > > There is a switch register on the SoC to decide which phy/mode is used. > By defaut is internal one with rmii mode. I think a driver is needed to > handle this properly. This sounds like a complex MDIO mux. You should think about this now, because others have left this same problem too late and ended up with a complex design in order to keep backwards compatibility with old DT blobs which don't actually describe the real hardware. Andrew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx 2024-11-01 12:40 ` Andrew Lunn @ 2024-11-02 0:49 ` Inochi Amaoto 0 siblings, 0 replies; 10+ messages in thread From: Inochi Amaoto @ 2024-11-02 0:49 UTC (permalink / raw) To: Andrew Lunn, Inochi Amaoto Cc: Chen Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou, Richard Cochran, Jisheng Zhang, Thomas Bonnefille, Liu Gui, Yixun Lan, Longbin Li, devicetree, linux-riscv, linux-kernel, netdev On Fri, Nov 01, 2024 at 01:40:00PM +0100, Andrew Lunn wrote: > > > > > > > + mdio { > > > > > > > + compatible = "snps,dwmac-mdio"; > > > > > > > + #address-cells = <1>; > > > > > > > + #size-cells = <0>; > > > > > > > + > > > > > > > + phy0: phy@0 { > > > > > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > > > > > + reg = <0>; > > > > > > > + }; > > > > > > > + }; > > > > > > > > > > > > It is not clear to me what cv18xx.dtsi represents, > > > > > > > > > > This is a include file to define common ip for the whole > > > > > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > > > > > > > > > and where the PHY node should be, here, or in a .dts file. > > > > > > Is this a SOM, and the PHY is on the SOM? > > > > > > > > > > The phy is on the SoC, it is embedded, and no external phy > > > > > is supported. So I think the phy node should stay here, not > > > > > in the dts file. > > > > > > > > There is a mistake, Some package supports external rmii/mii > > > > phy. So I will move this phy definition to board specific. > > > > > > When there is an external PHY, does the internal PHY still exists? If > > > it does, it should be listed, even if it is not used. > > > > > > Do the internal and external PHY share the same MDIO bus? > > > > They share the same MDIO bus and phy id setting. > > What do you mean by phy ID? > It is just part of the MDIO mux. Just ignore it. It is just used to show only one phy can be used at the same time. > > When an external phy > > is select, the internal one is not initialized and can not be accessed > > by the SoC. > > > > > I've seen some SoCs with complex MDIO muxes for internal vs external > > > PHYs. > > > > > > Andrew > > > > There is a switch register on the SoC to decide which phy/mode is used. > > By defaut is internal one with rmii mode. I think a driver is needed to > > handle this properly. > > This sounds like a complex MDIO mux. You should think about this now, > because others have left this same problem too late and ended up with > a complex design in order to keep backwards compatibility with old DT > blobs which don't actually describe the real hardware. > > Andrew Thanks, I wiil design a driver for it to handle this mux. Regards, Inochi ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-11-02 0:49 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-10-28 1:13 [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx Inochi Amaoto 2024-10-28 13:09 ` Andrew Lunn 2024-10-28 22:43 ` Inochi Amaoto 2024-10-29 2:50 ` Andrew Lunn 2024-10-29 3:36 ` Inochi Amaoto 2024-10-31 6:18 ` Inochi Amaoto 2024-10-31 13:04 ` Andrew Lunn 2024-10-31 22:46 ` Inochi Amaoto 2024-11-01 12:40 ` Andrew Lunn 2024-11-02 0:49 ` Inochi Amaoto
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®