[PATCH 0/4] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[PATCH 0/4] ARM: dts: imx6: phycore-som: PMIC and PHY fixes

[Primoz Fiser]

A few small fixes for the PHYTEC phyCORE-i.MX6 SOM:

- Pin the DA9062 PMIC watchdog to /dev/watchdog0 (1/4).
- Raise the PMIC's SOC/ARM buck ceiling to 1.5V, needed once the
  1.2GHz OPP tier ([1]] requests 1.3V for VDD_ARM and the anatop
  LDO's 125mV dropout is added on top (2/4).
- Migrate the Ethernet PHY reset off the deprecated fsl,fec.yaml
  phy-reset-gpios property onto the generic ethernet-phy.yaml
  reset-gpios/reset-assert-us binding (3/4, 4/4).

[1] https://lore.kernel.org/all/20260923070505.494949-1-primoz.fiser@norik.com/

Primoz Fiser (4):
  ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default
  ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage
  ARM: dts: imx6: phycore-som: Convert to generic PHY reset binding
  ARM: dts: imx6: phycore-som: Add reset-assert-us for PHY reset

 .../boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi   | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

-- 
2.34.1

[PATCH 1/4] ARM: dts: imx6: phycore-som: Set PMIC watchdog alias as default

[Primoz Fiser]

Pin the da9062 PMIC watchdog to /dev/watchdog0 via a DT alias, instead
of leaving it to be assigned dynamically by probe order. This SOM
already relies on the PMIC for reset (see commit aa4f48a4e06c ("ARM:
dts: imx6: phycore: Rely on PMIC reboot/reset handler")), so this
makes that the predictable, fixed watchdog device node.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index ddbfecd591f5..205467fd223e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -11,6 +11,7 @@ / {
 	aliases {
 		rtc1 = &da9062_rtc;
 		rtc2 = &snvs_rtc;
+		watchdog0 = &da9062_wdog;
 	};
 
 	/*
@@ -112,7 +113,7 @@ da9062_onkey: onkey {
 			compatible = "dlg,da9062-onkey";
 		};
 
-		watchdog {
+		da9062_wdog: watchdog {
 			compatible = "dlg,da9062-watchdog";
 			dlg,use-sw-pm;
 			dlg,wdt-sd = <1>;
-- 
2.34.1

[PATCH 2/4] ARM: dts: imx6: phycore-som: Increase PMIC max SOC and ARM voltage

[Primoz Fiser]

The i.MX 6Quad with 1.2 GHz needs 1.4-1.5 V supply voltage for the 1.2
GHz operating point. Therefore this patch increases the maximum output
voltage of the PMIC's SOC and ARM core supply regulators to 1.5 V.
Otherwise transition to 1.2 GHz OPP fails (with the 125 mV anatop LDO
dropout taken into account).

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 205467fd223e..9070388eecb0 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -133,7 +133,7 @@ regulators {
 			vdd_arm: buck1 {
 				regulator-name = "vdd_arm";
 				regulator-min-microvolt = <925000>;
-				regulator-max-microvolt = <1380000>;
+				regulator-max-microvolt = <1500000>;
 				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 				regulator-always-on;
 			};
@@ -141,7 +141,7 @@ vdd_arm: buck1 {
 			vdd_soc: buck2 {
 				regulator-name = "vdd_soc";
 				regulator-min-microvolt = <1150000>;
-				regulator-max-microvolt = <1380000>;
+				regulator-max-microvolt = <1500000>;
 				regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 				regulator-always-on;
 			};
-- 
2.34.1

[PATCH 3/4] ARM: dts: imx6: phycore-som: Convert to generic PHY reset binding

[Primoz Fiser]

The phy-reset-gpios property on the FEC node is deprecated by the
Documentation/devicetree/bindings/net/fsl,fec.yaml in favour of the
generic reset binding on the PHY node itself, described by the
Documentation/devicetree/bindings/net/ethernet-phy.yaml.

Move the reset GPIO from &fec to the ethphy child node as reset-gpios.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 9070388eecb0..88eabc7af6b7 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -56,7 +56,6 @@ &fec {
 	phy-handle = <&ethphy>;
 	phy-mode = "rgmii";
 	phy-supply = <&vdd_eth_io>;
-	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 	status = "disabled";
 
 	mdio {
@@ -65,6 +64,7 @@ mdio {
 
 		ethphy: ethernet-phy@3 {
 			reg = <3>;
+			reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 			txc-skew-ps = <1680>;
 			rxc-skew-ps = <1860>;
 		};
-- 
2.34.1

[PATCH 4/4] ARM: dts: imx6: phycore-som: Add reset-assert-us for PHY reset

[Primoz Fiser]

Without an explicit reset-assert-us, Ethernet PHY probing occasionally
fails. Set it to a 10 ms for a more robust PHY reset pulse.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
---
 arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 88eabc7af6b7..16e00375f474 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -65,6 +65,7 @@ mdio {
 		ethphy: ethernet-phy@3 {
 			reg = <3>;
 			reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
 			txc-skew-ps = <1680>;
 			rxc-skew-ps = <1860>;
 		};
-- 
2.34.1

Re: [PATCH 3/4] ARM: dts: imx6: phycore-som: Convert to generic PHY reset binding

[Frank Li]

On Wed, Sep 30, 2026 at 12:25:31PM +0200, Primoz Fiser wrote:
> The phy-reset-gpios property on the FEC node is deprecated by the
> Documentation/devicetree/bindings/net/fsl,fec.yaml in favour of the
> generic reset binding on the PHY node itself, described by the
> Documentation/devicetree/bindings/net/ethernet-phy.yaml.
>
> Move the reset GPIO from &fec to the ethphy child node as reset-gpios.

This movement may impact back compatiblity. Any other user use
phy-reset-gpios under $fec?

Frank

>
> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
> ---
>  arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
> index 9070388eecb0..88eabc7af6b7 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
> @@ -56,7 +56,6 @@ &fec {
>  	phy-handle = <&ethphy>;
>  	phy-mode = "rgmii";
>  	phy-supply = <&vdd_eth_io>;
> -	phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
>  	status = "disabled";
>
>  	mdio {
> @@ -65,6 +64,7 @@ mdio {
>
>  		ethphy: ethernet-phy@3 {
>  			reg = <3>;
> +			reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
>  			txc-skew-ps = <1680>;
>  			rxc-skew-ps = <1860>;
>  		};
> --
> 2.34.1
>
>