From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: "Arnd Bergmann" <arnd@arndb.de>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Linus Walleij" <linusw@kernel.org>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Michael Walle" <mwalle@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>, "Long Zhao" <zl020895@163.com>,
"Lee Jones" <lee@kernel.org>,
mfd@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 08/15] gpio: pl061: convert register access to regmap
Date: Fri, 2 Oct 2026 11:26:13 +0300 [thread overview]
Message-ID: <ar9qpeOCU0fpmhse@ashevche-desk.local> (raw)
In-Reply-To: <20261001-cv75-v5-v9-8-486cc289a4b8@ambarella.com>
On Thu, Oct 01, 2026 at 08:40:57PM +0800, Long Zhao via B4 Relay wrote:
> Replace readb()/writeb() with a MMIO regmap while keeping the existing
> gpio_chip and girq irqchip. Use a raw spinlock so irq_ack() can run
> under the irq descriptor lock.
...
> static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> + unsigned int gpiodir = 0;
>
> - if (readb(pl061->base + GPIODIR) & BIT(offset))
> + regmap_read(pl061->regmap, GPIODIR, &gpiodir);
Why not returning an error?
> + if (gpiodir & BIT(offset))
> return GPIO_LINE_DIRECTION_OUT;
>
> return GPIO_LINE_DIRECTION_IN;
I believe this can use regmap_test_bits().
...
> static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> unsigned long flags;
> - unsigned char gpiodir;
>
> raw_spin_lock_irqsave(&pl061->lock, flags);
> - gpiodir = readb(pl061->base + GPIODIR);
> - gpiodir &= ~(BIT(offset));
> - writeb(gpiodir, pl061->base + GPIODIR);
> + regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0);
_clear_bits()
> raw_spin_unlock_irqrestore(&pl061->lock, flags);
>
> return 0;
...
> static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> unsigned long flags;
> - unsigned char gpiodir;
> + unsigned int mask = BIT(offset);
>
> raw_spin_lock_irqsave(&pl061->lock, flags);
> - writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
> - gpiodir = readb(pl061->base + GPIODIR);
> - gpiodir |= BIT(offset);
> - writeb(gpiodir, pl061->base + GPIODIR);
> + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
> + !!value << offset);
_set_bits()
> + regmap_update_bits(pl061->regmap, GPIODIR, mask, mask);
>
> /*
> * gpio value is set again, because pl061 doesn't allow to set value of
> * a gpio pin before configuring it in OUT mode.
> */
> - writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
> + regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
> + !!value << offset);
Ditto.
> raw_spin_unlock_irqrestore(&pl061->lock, flags);
>
> return 0;
...
> static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
> static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> + unsigned int val = 0;
> +
> + regmap_read(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), &val);
>
> - return !!readb(pl061->base + (BIT(offset + 2)));
> + return !!val;
_test_bits()
> }
...
...and so on...
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-02 8:26 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 12:40 [PATCH v9 00/15] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-10-01 12:40 ` [PATCH v9 01/15] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-10-01 12:40 ` [PATCH v9 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-10-01 12:40 ` [PATCH v9 03/15] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-10-01 12:40 ` [PATCH v9 04/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-01 19:23 ` Conor Dooley
2026-10-01 19:36 ` Linus Walleij
2026-10-01 21:16 ` Conor Dooley
2026-10-01 12:40 ` [PATCH v9 05/15] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-10-01 12:40 ` [PATCH v9 06/15] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-10-02 8:10 ` Andy Shevchenko
2026-10-01 12:40 ` [PATCH v9 07/15] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-02 7:41 ` Andy Shevchenko
2026-10-01 12:40 ` [PATCH v9 08/15] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-02 8:26 ` Andy Shevchenko [this message]
2026-10-01 12:40 ` [PATCH v9 09/15] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-02 9:22 ` Andy Shevchenko
2026-10-01 12:40 ` [PATCH v9 10/15] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-01 12:41 ` [PATCH v9 11/15] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-01 12:41 ` [PATCH v9 12/15] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-01 12:41 ` [PATCH v9 13/15] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-10-01 12:52 ` Greg Kroah-Hartman
2026-10-01 19:20 ` Linus Walleij
2026-10-02 2:17 ` zl020895
2026-10-02 8:09 ` Jerome Brunet
2026-10-01 12:41 ` [PATCH v9 14/15] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-10-01 12:41 ` [PATCH v9 15/15] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
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