* [PATCH] clk: starfive: jh7110: Fix clk reference leak for pll0_out in jh7110_syscrg_probe()
@ 2026-09-09 4:43 blaze
2026-09-25 13:50 ` Brian Masney
0 siblings, 1 reply; 2+ messages in thread
From: blaze @ 2026-09-09 4:43 UTC (permalink / raw)
To: kernel, hal.feng; +Cc: linux-clk, linux-kernel, blaze
In jh7110_syscrg_probe(), the handling of the three PLL clock outputs
(pll0_out, pll1_out, pll2_out) follows the same pattern: clk_get() is
called, and on success clk_put() is called before setting the pll entry
to NULL. However, the pll0_out branch is missing clk_put(), unlike
pll1_out and pll2_out which correctly call clk_put(pllclk).
Additionally, when clk_notifier_register() fails, the error path returns
without releasing the clock reference, leaking it.
Fix this by calling clk_put(pllclk) after clk_notifier_register(),
matching the pattern used for pll1_out and pll2_out. Placing clk_put()
before the error check covers both the success and error paths.
Fixes: cc46f7c9edc4 ("clk: starfive: jh7110: Add PLL clock source support")
Signed-off-by: blaze <1466528493@qq.com>
---
drivers/clk/starfive/clk-starfive-jh7110-sys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 0000000..1111111 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -432,6 +432,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
+ clk_put(pllclk);
if (ret)
return ret;
priv->pll[0] = NULL;
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] clk: starfive: jh7110: Fix clk reference leak for pll0_out in jh7110_syscrg_probe()
2026-09-09 4:43 [PATCH] clk: starfive: jh7110: Fix clk reference leak for pll0_out in jh7110_syscrg_probe() blaze
@ 2026-09-25 13:50 ` Brian Masney
0 siblings, 0 replies; 2+ messages in thread
From: Brian Masney @ 2026-09-25 13:50 UTC (permalink / raw)
To: blaze; +Cc: kernel, hal.feng, linux-clk, linux-kernel
Hi blaze,
On Wed, Sep 09, 2026 at 12:43:31PM +0800, blaze wrote:
> In jh7110_syscrg_probe(), the handling of the three PLL clock outputs
> (pll0_out, pll1_out, pll2_out) follows the same pattern: clk_get() is
> called, and on success clk_put() is called before setting the pll entry
> to NULL. However, the pll0_out branch is missing clk_put(), unlike
> pll1_out and pll2_out which correctly call clk_put(pllclk).
>
> Additionally, when clk_notifier_register() fails, the error path returns
> without releasing the clock reference, leaking it.
>
> Fix this by calling clk_put(pllclk) after clk_notifier_register(),
> matching the pattern used for pll1_out and pll2_out. Placing clk_put()
> before the error check covers both the success and error paths.
>
> Fixes: cc46f7c9edc4 ("clk: starfive: jh7110: Add PLL clock source support")
> Signed-off-by: blaze <1466528493@qq.com>
> ---
> drivers/clk/starfive/clk-starfive-jh7110-sys.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 0000000..1111111 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -432,6 +432,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
> priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
> ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
> + clk_put(pllclk);
> if (ret)
> return ret;
> priv->pll[0] = NULL;
> --
> 2.43.0
This patch is malformed and won't apply. You should consider using b4:
https://b4.docs.kernel.org/en/latest/contributor/send.html
Brian
^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-09-09 4:43 [PATCH] clk: starfive: jh7110: Fix clk reference leak for pll0_out in jh7110_syscrg_probe() blaze
2026-09-25 13:50 ` Brian Masney
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