From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org, Chanho Min <chanho.min@lge.com>
Subject: Re: [PATCH v11 4/9] gpio: pl061: convert register access to regmap
Date: Wed, 21 Oct 2026 15:47:09 +0300 [thread overview]
Message-ID: <ati0TWJWwEo1W2UE@ashevche-desk.local> (raw)
In-Reply-To: <20261020-cv75-gpio-v11-4-e058bae19571@ambarella.com>
On Tue, Oct 20, 2026 at 03:54:08PM +0800, Long Zhao via B4 Relay wrote:
> Replace readb()/writeb() with a MMIO regmap while keeping the existing
> gpio_chip and girq irqchip. Use a raw spinlock so irq_ack() can run
> under the irq descriptor lock.
...
> static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> unsigned long flags;
> - unsigned char gpiodir;
> + unsigned int mask = BIT(offset);
Please, check everywhere (where you touch the definition blocks)
if you follow reversed xmas tree order. No need to resend just for
it, but if anything requires v12, please also address this.
> raw_spin_lock_irqsave(&pl061->lock, flags);
...
> static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value)
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
>
> - writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
> -
> - return 0;
> + return regmap_assign_bits(pl061->regmap,
> + BIT(offset + PL061_DATA_OFFSET),
Keep it on a single (81 characters) line, it's fine, it keeps it consistent
with the rest of the similar calls, so increases readability overall of the
driver. With the same remark, address if you need a v12 for something else.
> + BIT(offset), value);
> }
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-21 12:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 7:54 [PATCH v11 0/9] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 1/9] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 2/9] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 3/9] gpio: pl061: drop redundant pending check in the IRQ handler Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 4/9] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-21 12:47 ` Andy Shevchenko [this message]
2026-10-20 7:54 ` [PATCH v11 5/9] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 6/9] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-21 16:13 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 7/9] gpio: pl061: keep the parent device in a local Long Zhao via B4 Relay
2026-10-21 17:27 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 8/9] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-21 17:41 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 9/9] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
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