From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v11 8/9] gpio: pl061: switch data path to gpio-regmap
Date: Wed, 21 Oct 2026 20:41:24 +0300 [thread overview]
Message-ID: <atj5RLO6PYLiFgOs@ashevche-desk.local> (raw)
In-Reply-To: <20261020-cv75-gpio-v11-8-e058bae19571@ambarella.com>
On Tue, Oct 20, 2026 at 03:54:12PM +0800, Long Zhao via B4 Relay wrote:
> Move get, set and direction onto gpio-regmap. ARM PL061 sets
> GPIO_REGMAP_QUIRK_SET_AFTER_DIR so the output value is written
> after the direction change.
>
> Keep a custom irqchip and irq domain. Create the domain with
> the PL061 private data and let gpio-regmap attach it.
>
> Check the chained-handler regmap_read() return and always run
> chained_irq_exit(). irq_type still ignores MMIO write returns.
>
> irq_set_parent() nests the GPIO irq_desc under the AMBA parent
> for irq_set_wake() and lockdep; checked with PROVE_LOCKING on
> CV75.
...
> static void pl061_irq_handler(struct irq_desc *desc)
> {
> + struct pl061 *pl061 = irq_desc_get_handler_data(desc);
> + struct irq_chip *irqchip = irq_desc_get_chip(desc);
> unsigned long pending;
> unsigned int mis = 0;
> int offset;
> - struct gpio_chip *gc = irq_desc_get_handler_data(desc);
> - struct pl061 *pl061 = gpiochip_get_data(gc);
> - struct irq_chip *irqchip = irq_desc_get_chip(desc);
> + int ret;
>
> chained_irq_enter(irqchip, desc);
>
> - regmap_read(pl061->regmap, GPIOMIS, &mis);
> + ret = regmap_read(pl061->regmap, pl061->data->regs->mis, &mis);
> + if (ret)
> + goto out;
I think error checking is not required as we have mis = 0 still, so
the failed regmap_read() shouldn't change that.
> pending = mis;
> - for_each_set_bit(offset, &pending, PL061_GPIO_NR)
> - generic_handle_domain_irq(gc->irq.domain, offset);
> + for_each_set_bit(offset, &pending, pl061->data->ngpio)
> + generic_handle_domain_irq(pl061->irq_domain, offset);
>
> +out:
> chained_irq_exit(irqchip, desc);
> }
...
> + for (unsigned int i = 0; i < pl061->data->ngpio; i++) {
> + unsigned int virq;
> +
> + virq = irq_find_mapping(pl061->irq_domain, i);
> + if (virq)
Unneeded checkm it's already inside the below call.
> + irq_dispose_mapping(virq);
So, altogether
for (unsigned int i = 0; i < pl061->data->ngpio; i++)
irq_dispose_mapping(irq_find_mapping(pl061->irq_domain, i));
> + }
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-21 17:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 7:54 [PATCH v11 0/9] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 1/9] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 2/9] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 3/9] gpio: pl061: drop redundant pending check in the IRQ handler Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 4/9] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-21 12:47 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 5/9] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-20 7:54 ` [PATCH v11 6/9] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-21 16:13 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 7/9] gpio: pl061: keep the parent device in a local Long Zhao via B4 Relay
2026-10-21 17:27 ` Andy Shevchenko
2026-10-20 7:54 ` [PATCH v11 8/9] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-21 17:41 ` Andy Shevchenko [this message]
2026-10-20 7:54 ` [PATCH v11 9/9] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
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