[PATCH RFC 0/3] arm64: dts: qcom: Add Ethernet support for Nord

[PATCH RFC 0/3] arm64: dts: qcom: Add Ethernet support for Nord

[Shawn Guo]

Describe both 10-Gbps Ethernet controllers on Nord and enable them on the
RRD and Ride embedded boards.

The SoC description adds the two EMAC instances (qcom,nord-ethqos) and
their XPCS blocks, plus the SGMII/USXGMII SerDes PHYs they use. Each
controller gets its clocks, reset, power domain, interconnect paths,
SMMU stream IDs and DMA queue configuration.

Patch 2 enables both ports on Nord Ride in fixed-link USXGMII 10 Gbps mode,
for the onboard firmware-driven Ethernet switch. Patch 3 enables both ports
on Nord RRD, each connected over USXGMII to an Aquantia AQR113C PHY on the
controller's MDIO bus, with PHY interrupt and reset GPIOs.

Dependencies:
- [PATCH 0/3] phy: qcom: sgmii-eth: add Nord USXGMII support
  https://lore.kernel.org/all/20260923-nord_ethernet_serdes-v1-0-f8ac1c487882@oss.qualcomm.com/
- [PATCH RFC net-next 0/9] net: introduce Qualcomm XPCS support and add Nord Ethernet plumbing
  https://lore.kernel.org/all/20260923-qcom_xpcs_nord_emac-v1-0-4b1c682af70f@oss.qualcomm.com/
- [PATCH 0/3] Nord ethernet followup
  https://lore.kernel.org/all/20260923084921.3942100-1-zhangfei.gao@oss.qualcomm.com/
- [PATCH v5 0/7] arm64: dts: qcom: nord: Add remoteproc and PMIC support
  https://lore.kernel.org/all/20261014063953.549379-1-shengchao.guo@oss.qualcomm.com/

Mohd Ayaan Anwar (2):
  arm64: dts: qcom: nord: Add Ethernet support
  arm64: dts: qcom: nord-ride-embedded: Enable Ethernet

Zhangfei Gao (1):
  arm64: dts: qcom: nord-rrd: Enable Ethernet

 arch/arm64/boot/dts/qcom/nord-embedded.dtsi   | 124 ++++++++
 .../boot/dts/qcom/nord-ride-embedded.dts      |  44 +++
 arch/arm64/boot/dts/qcom/nord-rrd.dts         |  88 ++++++
 arch/arm64/boot/dts/qcom/nord.dtsi            | 282 ++++++++++++++++++
 4 files changed, 538 insertions(+)

-- 
2.43.0

[PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Shawn Guo]

From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>

Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
and DMA queues.

Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 124 +++++++++
 arch/arm64/boot/dts/qcom/nord.dtsi          | 282 ++++++++++++++++++++
 2 files changed, 406 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 6dc4c871f41e..72094c84e346 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -42,6 +42,60 @@ &crypto {
 	status = "okay";
 };
 
+&ethernet0 {
+	clocks = <&segcc SE_GCC_EMAC0_AXI_CLK>,
+		 <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>,
+		 <&segcc SE_GCC_EMAC0_PTP_CLK>,
+		 <&segcc SE_GCC_EMAC0_PHY_AUX_CLK>,
+		 <&segcc SE_GCC_EEE_EMAC0_CLK>;
+	clock-names = "stmmaceth",
+		      "pclk",
+		      "ptp_ref",
+		      "phyaux",
+		      "eee";
+
+	resets = <&segcc SE_GCC_EMAC0_BCR>;
+
+	power-domains = <&segcc SE_GCC_EMAC0_GDSC>;
+
+	interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+			 &config_noc SLAVE_PS_ETH_0 QCOM_ICC_TAG_ALWAYS>,
+			<&aggre2_noc_tile MASTER_EMAC_0 QCOM_ICC_TAG_ALWAYS
+			 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+	interconnect-names = "cpu-mac",
+			     "mac-mem";
+
+	phys = <&serdes0>;
+	phy-names = "serdes";
+};
+
+&ethernet1 {
+	clocks = <&segcc SE_GCC_EMAC1_AXI_CLK>,
+		 <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>,
+		 <&segcc SE_GCC_EMAC1_PTP_CLK>,
+		 <&segcc SE_GCC_EMAC1_PHY_AUX_CLK>,
+		 <&segcc SE_GCC_EEE_EMAC1_CLK>;
+	clock-names = "stmmaceth",
+		      "pclk",
+		      "ptp_ref",
+		      "phyaux",
+		      "eee";
+
+	resets = <&segcc SE_GCC_EMAC1_BCR>;
+
+	power-domains = <&segcc SE_GCC_EMAC1_GDSC>;
+
+	interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+			 &config_noc SLAVE_PS_ETH_1 QCOM_ICC_TAG_ALWAYS>,
+			<&aggre2_noc_tile MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS
+			 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+	interconnect-names = "cpu-mac",
+			     "mac-mem";
+
+	phys = <&serdes1>;
+	phy-names = "serdes";
+};
+
 &i2c0 {
 	clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>;
 	clock-names = "se";
@@ -857,6 +911,30 @@ hpass_ag_noc: interconnect@5fc0000 {
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
+	serdes0: phy@88f8000 {
+		compatible = "qcom,nord-dwmac-sgmii-phy";
+		reg = <0x0 0x088f8000 0x0 0x4000>;
+
+		clocks = <&tcsrcc TCSR_UX_SGMII_0_CLKREF_EN>;
+		clock-names = "sgmi_ref";
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+
+	serdes1: phy@88fc000 {
+		compatible = "qcom,nord-dwmac-sgmii-phy";
+		reg = <0x0 0x088fc000 0x0 0x4000>;
+
+		clocks = <&tcsrcc TCSR_UX_SGMII_1_CLKREF_EN>;
+		clock-names = "sgmi_ref";
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+
 	negcc: clock-controller@8900000 {
 		compatible = "qcom,nord-negcc";
 		reg = <0x0 0x08900000 0x0 0xf4200>;
@@ -1106,6 +1184,38 @@ nsp_data_noc_3: interconnect@1fe00000 {
 };
 
 &tlmm {
+	ethernet0_default: ethernet0-default-state {
+		mdc-pins {
+			pins = "gpio47";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio48";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+
+	ethernet1_default: ethernet1-default-state {
+		mdc-pins {
+			pins = "gpio49";
+			function = "emac1_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio50";
+			function = "emac1_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+
 	qup_i2c0_default: qup-i2c0-default-state {
 		pins = "gpio111", "gpio112";
 		function = "qup0_se0";
@@ -1989,3 +2099,17 @@ opp-403000000 {
 		};
 	};
 };
+
+&xpcs0 {
+	clocks = <&segcc SE_GCC_EMAC0_CNOC_APB_CLK>;
+	clock-names = "csr";
+
+	power-domains = <&segcc SE_GCC_EMAC0_GDSC>;
+};
+
+&xpcs1 {
+	clocks = <&segcc SE_GCC_EMAC1_CNOC_APB_CLK>;
+	clock-names = "csr";
+
+	power-domains = <&segcc SE_GCC_EMAC1_GDSC>;
+};
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index dfbbaf94a7ae..586fedd2580d 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1593,6 +1593,288 @@ rng: rng@10c3000 {
 			reg = <0x0 0x010c3000 0x0 0x1000>;
 		};
 
+		ethernet0: ethernet@1a00000 {
+			compatible = "qcom,nord-ethqos";
+
+			reg = <0x0 0x01a00000 0x0 0x14000>,
+			      <0x0 0x01a7f000 0x0 0x1000>;
+			reg-names = "stmmaceth",
+				    "rgmii";
+
+			interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "eth_lpi";
+
+			iommus = <&apps_smmu_2 0x1201 0x2>,
+				 <&apps_smmu_2 0x1202 0x0>,
+				 <&apps_smmu_2 0x1203 0x2>,
+				 <&apps_smmu_2 0x1204 0x0>,
+				 <&apps_smmu_2 0x1205 0x2>,
+				 <&apps_smmu_2 0x1206 0x0>,
+				 <&apps_smmu_2 0x1207 0x2>,
+				 <&apps_smmu_2 0x1208 0x0>,
+				 <&apps_smmu_2 0x1209 0x0>,
+				 <&apps_smmu_2 0x120a 0x0>;
+
+			pcs-handle = <&xpcs0>;
+
+			dma-coherent;
+
+			rx-fifo-depth = <98304>;
+			tx-fifo-depth = <98304>;
+
+			snps,tso;
+			snps,pbl = <16>;
+			snps,axi-config = <&emac0_axi_setup>;
+			snps,mtl-rx-config = <&emac0_mtl_rx>;
+			snps,mtl-tx-config = <&emac0_mtl_tx>;
+
+			status = "disabled";
+
+			emac0_axi_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <16>;
+				snps,rd_osr_lmt = <16>;
+				snps,blen = <0 0 0 0 16 0 0>;
+			};
+
+			emac0_mtl_rx: rx-queues-config {
+				snps,rx-queues-to-use = <8>;
+				snps,rx-sched-sp;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+					snps,route-up;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x1>;
+					snps,route-ptp;
+				};
+
+				queue2 {
+					snps,avb-algorithm;
+					snps,map-to-dma-channel = <0x2>;
+					snps,route-avcp;
+				};
+
+				queue3 {
+					snps,avb-algorithm;
+					snps,map-to-dma-channel = <0x3>;
+					snps,priority = <0xc>;
+				};
+
+				queue4 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x4>;
+				};
+
+				queue5 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x5>;
+				};
+
+				queue6 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x6>;
+				};
+
+				queue7 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x7>;
+				};
+			};
+
+			emac0_mtl_tx: tx-queues-config {
+				snps,tx-queues-to-use = <8>;
+
+				queue0 {
+					snps,dcb-algorithm;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+				};
+
+				queue4 {
+					snps,dcb-algorithm;
+				};
+
+				queue5 {
+					snps,dcb-algorithm;
+				};
+
+				queue6 {
+					snps,dcb-algorithm;
+				};
+
+				queue7 {
+					snps,dcb-algorithm;
+				};
+			};
+		};
+
+		xpcs0: xpcs@1a14000 {
+			compatible = "qcom,nord-dw-xpcs";
+
+			reg = <0x0 0x01a14000 0x0 0x5100>;
+			reg-names = "direct";
+			reg-io-width = <4>;
+
+			status = "disabled";
+		};
+
+		ethernet1: ethernet@1a80000 {
+			compatible = "qcom,nord-ethqos";
+
+			reg = <0x0 0x01a80000 0x0 0x14000>,
+			      <0x0 0x01aff000 0x0 0x1000>;
+			reg-names = "stmmaceth",
+				    "rgmii";
+
+			interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq",
+					  "eth_lpi";
+
+			iommus = <&apps_smmu_2 0x11c1 0x8>,
+				 <&apps_smmu_2 0x11c2 0x1>,
+				 <&apps_smmu_2 0x11c3 0x1>,
+				 <&apps_smmu_2 0x11c4 0x3>,
+				 <&apps_smmu_2 0x11c5 0x3>,
+				 <&apps_smmu_2 0x11c6 0x3>,
+				 <&apps_smmu_2 0x11c7 0x3>,
+				 <&apps_smmu_2 0x11c8 0x2>,
+				 <&apps_smmu_2 0x11c9 0x8>,
+				 <&apps_smmu_2 0x11ca 0x2>;
+
+			pcs-handle = <&xpcs1>;
+
+			dma-coherent;
+
+			rx-fifo-depth = <98304>;
+			tx-fifo-depth = <98304>;
+
+			snps,tso;
+			snps,pbl = <16>;
+			snps,axi-config = <&emac1_axi_setup>;
+			snps,mtl-rx-config = <&emac1_mtl_rx>;
+			snps,mtl-tx-config = <&emac1_mtl_tx>;
+
+			status = "disabled";
+
+			emac1_axi_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <16>;
+				snps,rd_osr_lmt = <16>;
+				snps,blen = <0 0 0 0 16 0 0>;
+			};
+
+			emac1_mtl_rx: rx-queues-config {
+				snps,rx-queues-to-use = <8>;
+				snps,rx-sched-sp;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+					snps,route-up;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x1>;
+					snps,route-ptp;
+				};
+
+				queue2 {
+					snps,avb-algorithm;
+					snps,map-to-dma-channel = <0x2>;
+					snps,route-avcp;
+				};
+
+				queue3 {
+					snps,avb-algorithm;
+					snps,map-to-dma-channel = <0x3>;
+					snps,priority = <0xc>;
+				};
+
+				queue4 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x4>;
+				};
+
+				queue5 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x5>;
+				};
+
+				queue6 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x6>;
+				};
+
+				queue7 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x7>;
+				};
+			};
+
+			emac1_mtl_tx: tx-queues-config {
+				snps,tx-queues-to-use = <8>;
+
+				queue0 {
+					snps,dcb-algorithm;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+				};
+
+				queue4 {
+					snps,dcb-algorithm;
+				};
+
+				queue5 {
+					snps,dcb-algorithm;
+				};
+
+				queue6 {
+					snps,dcb-algorithm;
+				};
+
+				queue7 {
+					snps,dcb-algorithm;
+				};
+			};
+		};
+
+		xpcs1: xpcs@1a94000 {
+			compatible = "qcom,nord-dw-xpcs";
+
+			reg = <0x0 0x01a94000 0x0 0x5100>;
+			reg-names = "direct";
+			reg-io-width = <4>;
+
+			status = "disabled";
+		};
+
 		ufs_mem_hc: ufshc@1d44000 {
 			compatible = "qcom,nord-ufshc",
 				     "qcom,ufshc",
-- 
2.43.0

[PATCH RFC 2/3] arm64: dts: qcom: nord-ride-embedded: Enable Ethernet

[Shawn Guo]

From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>

Enable both Ethernet ports on Nord Ride in fixed-link USXGMII 10-Gbps
mode for connection to the onboard firmware driven Ethernet switch.

Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 .../boot/dts/qcom/nord-ride-embedded.dts      | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
index 49635695f832..50bf4c32641d 100644
--- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
+++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
@@ -366,6 +366,28 @@ vreg_l3l_1p8: ldo3 {
 	};
 };
 
+&ethernet0 {
+	phy-mode = "usxgmii";
+
+	status = "okay";
+
+	fixed-link {
+		speed = <10000>;
+		full-duplex;
+	};
+};
+
+&ethernet1 {
+	phy-mode = "usxgmii";
+
+	status = "okay";
+
+	fixed-link {
+		speed = <10000>;
+		full-duplex;
+	};
+};
+
 &qupv3_0 {
 	firmware-name = "qcom/nord/qupv3fw.elf";
 
@@ -419,6 +441,20 @@ &remoteproc_cdsp3 {
 	status = "okay";
 };
 
+&serdes0 {
+	vdda-0p9-supply = <&vreg_l1h_0p9>;
+	vdda-1p2-supply = <&vreg_l2h_1p2>;
+
+	status = "okay";
+};
+
+&serdes1 {
+	vdda-0p9-supply = <&vreg_l1h_0p9>;
+	vdda-1p2-supply = <&vreg_l2h_1p2>;
+
+	status = "okay";
+};
+
 &uart15 {
 	status = "okay";
 };
@@ -440,3 +476,11 @@ &ufs_mem_phy {
 
 	status = "okay";
 };
+
+&xpcs0 {
+	status = "okay";
+};
+
+&xpcs1 {
+	status = "okay";
+};
-- 
2.43.0

[PATCH RFC 3/3] arm64: dts: qcom: nord-rrd: Enable Ethernet

[Shawn Guo]

From: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com>

Enable both Ethernet ports on the Nord RRD board, each connected over
USXGMII to an Aquantia AQR113C PHY managed through the controller's MDIO
bus.

Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/nord-rrd.dts | 88 +++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts
index 47978df0af92..0f6259d91c42 100644
--- a/arch/arm64/boot/dts/qcom/nord-rrd.dts
+++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts
@@ -366,6 +366,56 @@ vreg_l3l_1p8: ldo3 {
 	};
 };
 
+&ethernet0 {
+	pinctrl-0 = <&ethernet0_default>, <&ethernet0_phy_int>;
+	pinctrl-names = "default";
+
+	phy-mode = "usxgmii";
+	phy-handle = <&sgmii_phy0>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sgmii_phy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-id31c3.1c12";
+			reg = <0x0>;
+			interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmau0102_e_gpios 5 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+};
+
+&ethernet1 {
+	pinctrl-0 = <&ethernet1_default>, <&ethernet1_phy_int>;
+	pinctrl-names = "default";
+
+	phy-mode = "usxgmii";
+	phy-handle = <&sgmii_phy1>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sgmii_phy1: ethernet-phy@8 {
+			compatible = "ethernet-phy-id31c3.1c12";
+			reg = <0x8>;
+			interrupts-extended = <&tlmm 55 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&pmau0102_f_gpios 7 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+};
+
 &i2c7 {
 	clock-frequency = <400000>;
 
@@ -430,10 +480,40 @@ &remoteproc_cdsp3 {
 	status = "okay";
 };
 
+&serdes0 {
+	vdda-0p9-supply = <&vreg_l1h_0p9>;
+	vdda-1p2-supply = <&vreg_l2h_1p2>;
+
+	status = "okay";
+};
+
+&serdes1 {
+	vdda-0p9-supply = <&vreg_l1h_0p9>;
+	vdda-1p2-supply = <&vreg_l2h_1p2>;
+
+	status = "okay";
+};
+
 &spi16 {
 	status = "okay";
 };
 
+&tlmm {
+	ethernet0_phy_int: ethernet0-phy-int-state {
+		pins = "gpio141";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	ethernet1_phy_int: ethernet1-phy-int-state {
+		pins = "gpio55";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};
+
 &uart4 {
 	status = "okay";
 };
@@ -459,3 +539,11 @@ &ufs_mem_phy {
 
 	status = "okay";
 };
+
+&xpcs0 {
+	status = "okay";
+};
+
+&xpcs1 {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Konrad Dybcio]

On 11/1/26 9:04 AM, Shawn Guo wrote:
> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> 
> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> and DMA queues.
> 
> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---

[...]

> +	phys = <&serdes0>;
> +	phy-names = "serdes";

I believe this holds for both GearVM and embedded, so you can move
it to the common DTSI

Konrad

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Konrad Dybcio]

On 11/1/26 9:04 AM, Shawn Guo wrote:
> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> 
> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> and DMA queues.
> 
> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---

I think we can't enable the ethernet hosts indiscrimately (I would
love to be corrected here!), can we keep the XPCS nodes enabled by
default?

Konrad

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Shawn Guo]

On Mon, Nov 02, 2026 at 04:01:03PM +0100, Konrad Dybcio wrote:
> On 11/1/26 9:04 AM, Shawn Guo wrote:
> > From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> > 
> > Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> > SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> > and DMA queues.
> > 
> > Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> > +	phys = <&serdes0>;
> > +	phy-names = "serdes";
> 
> I believe this holds for both GearVM and embedded, so you can move
> it to the common DTSI

No, this doesn't apply to GearVM. The SerDes is owned entirely by the SCMI
server firmware for GearVM variant. LDOs, clkref, reset, and the per-speed
PLL/RX/TX programming driven by an SCMI perf domain whose level is
the link speed.

Shawn

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Konrad Dybcio]

On 11/4/26 8:59 AM, Shawn Guo wrote:
> On Mon, Nov 02, 2026 at 04:01:03PM +0100, Konrad Dybcio wrote:
>> On 11/1/26 9:04 AM, Shawn Guo wrote:
>>> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
>>>
>>> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
>>> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
>>> and DMA queues.
>>>
>>> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
>>> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +	phys = <&serdes0>;
>>> +	phy-names = "serdes";
>>
>> I believe this holds for both GearVM and embedded, so you can move
>> it to the common DTSI
> 
> No, this doesn't apply to GearVM. The SerDes is owned entirely by the SCMI
> server firmware for GearVM variant. LDOs, clkref, reset, and the per-speed
> PLL/RX/TX programming driven by an SCMI perf domain whose level is
> the link speed.

Right, but I meant the assignment to the EMACs specifically

Konrad

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Shawn Guo]

On Wed, Nov 04, 2026 at 09:04:33AM +0100, Konrad Dybcio wrote:
> On 11/4/26 8:59 AM, Shawn Guo wrote:
> > On Mon, Nov 02, 2026 at 04:01:03PM +0100, Konrad Dybcio wrote:
> >> On 11/1/26 9:04 AM, Shawn Guo wrote:
> >>> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> >>>
> >>> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> >>> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> >>> and DMA queues.
> >>>
> >>> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> >>> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> +	phys = <&serdes0>;
> >>> +	phy-names = "serdes";
> >>
> >> I believe this holds for both GearVM and embedded, so you can move
> >> it to the common DTSI
> > 
> > No, this doesn't apply to GearVM. The SerDes is owned entirely by the SCMI
> > server firmware for GearVM variant. LDOs, clkref, reset, and the per-speed
> > PLL/RX/TX programming driven by an SCMI perf domain whose level is
> > the link speed.
> 
> Right, but I meant the assignment to the EMACs specifically

The EMAC0/SerDes0 and EMAC1/SerDes1 pairing is indeed the same on both
variants. But the serdes nodes only exist in nord-embedded.dtsi, since
GearVM doesn't expose the PHY to Linux. Or am I missing your point
completely?

Shawn

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Konrad Dybcio]

On 11/4/26 9:42 AM, Shawn Guo wrote:
> On Wed, Nov 04, 2026 at 09:04:33AM +0100, Konrad Dybcio wrote:
>> On 11/4/26 8:59 AM, Shawn Guo wrote:
>>> On Mon, Nov 02, 2026 at 04:01:03PM +0100, Konrad Dybcio wrote:
>>>> On 11/1/26 9:04 AM, Shawn Guo wrote:
>>>>> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
>>>>>
>>>>> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
>>>>> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
>>>>> and DMA queues.
>>>>>
>>>>> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
>>>>> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>>>>> ---
>>>>
>>>> [...]
>>>>
>>>>> +	phys = <&serdes0>;
>>>>> +	phy-names = "serdes";
>>>>
>>>> I believe this holds for both GearVM and embedded, so you can move
>>>> it to the common DTSI
>>>
>>> No, this doesn't apply to GearVM. The SerDes is owned entirely by the SCMI
>>> server firmware for GearVM variant. LDOs, clkref, reset, and the per-speed
>>> PLL/RX/TX programming driven by an SCMI perf domain whose level is
>>> the link speed.
>>
>> Right, but I meant the assignment to the EMACs specifically
> 
> The EMAC0/SerDes0 and EMAC1/SerDes1 pairing is indeed the same on both
> variants. But the serdes nodes only exist in nord-embedded.dtsi, since
> GearVM doesn't expose the PHY to Linux. Or am I missing your point
> completely?

No, I was just completely sure that the nodes exist in the gvm one too
because it seems like they do on lemans:

https://lore.kernel.org/linux-arm-msm/20261103-sa8255p-eth-phy-v18-1-b00cc2fa0404@oss.qualcomm.com/

Konrad

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Shawn Guo]

On Mon, Nov 02, 2026 at 04:03:08PM +0100, Konrad Dybcio wrote:
> On 11/1/26 9:04 AM, Shawn Guo wrote:
> > From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> > 
> > Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> > SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> > and DMA queues.
> > 
> > Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> 
> I think we can't enable the ethernet hosts indiscrimately (I would
> love to be corrected here!), can we keep the XPCS nodes enabled by
> default?

Yes, we can. I will enable them in nord-embedded.dtsi instead of nord.dtsi
(to avoid CHECK_DTBS complaints on GearVM variant).

Shawn

Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add Ethernet support

[Shawn Guo]

On Wed, Nov 04, 2026 at 10:04:00AM +0100, Konrad Dybcio wrote:
> On 11/4/26 9:42 AM, Shawn Guo wrote:
> > On Wed, Nov 04, 2026 at 09:04:33AM +0100, Konrad Dybcio wrote:
> >> On 11/4/26 8:59 AM, Shawn Guo wrote:
> >>> On Mon, Nov 02, 2026 at 04:01:03PM +0100, Konrad Dybcio wrote:
> >>>> On 11/1/26 9:04 AM, Shawn Guo wrote:
> >>>>> From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> >>>>>
> >>>>> Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and
> >>>>> SerDes blocks, clocks, resets, power domains, interconnects, SMMU streams
> >>>>> and DMA queues.
> >>>>>
> >>>>> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
> >>>>> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> >>>>> ---
> >>>>
> >>>> [...]
> >>>>
> >>>>> +	phys = <&serdes0>;
> >>>>> +	phy-names = "serdes";
> >>>>
> >>>> I believe this holds for both GearVM and embedded, so you can move
> >>>> it to the common DTSI
> >>>
> >>> No, this doesn't apply to GearVM. The SerDes is owned entirely by the SCMI
> >>> server firmware for GearVM variant. LDOs, clkref, reset, and the per-speed
> >>> PLL/RX/TX programming driven by an SCMI perf domain whose level is
> >>> the link speed.
> >>
> >> Right, but I meant the assignment to the EMACs specifically
> > 
> > The EMAC0/SerDes0 and EMAC1/SerDes1 pairing is indeed the same on both
> > variants. But the serdes nodes only exist in nord-embedded.dtsi, since
> > GearVM doesn't expose the PHY to Linux. Or am I missing your point
> > completely?
> 
> No, I was just completely sure that the nodes exist in the gvm one too
> because it seems like they do on lemans:
> 
> https://lore.kernel.org/linux-arm-msm/20261103-sa8255p-eth-phy-v18-1-b00cc2fa0404@oss.qualcomm.com/

Ah, right! We will likely have it for Nord GearVM variant as well,
so your suggestion makes sense. I will update.

Shawn