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* [PATCH v1 1/1] ASoC: wm8904: Enable FLL when switching an active SYSCLK to FLL
@ 2026-11-04 15:58 Stefano Radaelli
  2026-11-04 16:26 ` Charles Keepax
  2026-11-04 18:37 ` Mark Brown
  0 siblings, 2 replies; 3+ messages in thread
From: Stefano Radaelli @ 2026-11-04 15:58 UTC (permalink / raw)
  To: linux-kernel, linux-sound
  Cc: pierluigi.p, alexander.h, Stefano Radaelli, Liam Girdwood,
	Mark Brown, Jaroslav Kysela, Takashi Iwai, Charles Keepax,
	Kuninori Morimoto, Linus Walleij, Kees Cook,
	Uwe Kleine-König (The Capable Hub),
	patches

From: Stefano Radaelli <stefano.r@variscite.com>

When switching SYSCLK from MCLK to FLL, DAPM may keep SYSCLK powered
and skip the PRE_PMU event that normally enables the FLL. This leaves
SYSCLK sourced from a disabled FLL and can cause playback to fail.

Enable FLL_OSC_ENA and FLL_ENA before selecting FLL as the SYSCLK
source when WM8904_CLK_SYS_ENA is already set.

On VAR-SOM-MX8X, playing audio at 48 kHz followed immediately by
8 kHz reproduced an I/O error when switching from MCLK to FLL.
With this change, playback succeeds.

Co-developed-by: Alexander Herfurtner <alexander.h@variscite.com>
Signed-off-by: Alexander Herfurtner <alexander.h@variscite.com>
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
 sound/soc/codecs/wm8904.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 96d2e54a2c6a..efa108544927 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -338,6 +338,20 @@ static int wm8904_configure_clocking(struct snd_soc_component *component)
 		dev_dbg(component->dev, "Using %dHz FLL clock\n",
 			wm8904->fll_fout);
 
+		/* The SYSCLK may already be on; if source changes to FLL, ensure
+		 * FLL is enabled before selecting it as SYSCLK source.
+		 */
+		if (clock2 & WM8904_CLK_SYS_ENA) {
+			snd_soc_component_update_bits(component,
+						      WM8904_FLL_CONTROL_1,
+						      WM8904_FLL_OSC_ENA,
+						      WM8904_FLL_OSC_ENA);
+			snd_soc_component_update_bits(component,
+						      WM8904_FLL_CONTROL_1,
+						      WM8904_FLL_ENA,
+						      WM8904_FLL_ENA);
+		}
+
 		clock2 |= WM8904_SYSCLK_SRC;
 		rate = wm8904->fll_fout;
 		break;
-- 
2.47.3


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2026-11-04 23:39 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2026-11-04 15:58 [PATCH v1 1/1] ASoC: wm8904: Enable FLL when switching an active SYSCLK to FLL Stefano Radaelli
2026-11-04 16:26 ` Charles Keepax
2026-11-04 18:37 ` Mark Brown

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