From: Julia Cartwright <julia@ni.com>
To: Linus Walleij <linus.walleij@linaro.org>, Barry Song <baohua@kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
<linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 18/19] pinctrl: sirf: atlas7: make use of raw_spinlock variants
Date: Thu, 9 Mar 2017 10:22:05 -0600 [thread overview]
Message-ID: <c68b030b8903bb1ca2f501b2e5c651d9206b1133.1489015238.git.julia@ni.com> (raw)
In-Reply-To: <cover.1489015238.git.julia@ni.com>
The sirf atlas7 pinctrl drivers currently implement an irq_chip for
handling interrupts; due to how irq_chip handling is done, it's
necessary for the irq_chip methods to be invoked from hardirq context,
even on a a real-time kernel. Because the spinlock_t type becomes a
"sleeping" spinlock w/ RT kernels, it is not suitable to be used with
irq_chips.
A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: Julia Cartwright <julia@ni.com>
---
drivers/pinctrl/sirf/pinctrl-atlas7.c | 44 +++++++++++++++++------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 600d6427a978..1efa315a7dbe 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -352,7 +352,7 @@ struct atlas7_gpio_chip {
void __iomem *reg;
struct clk *clk;
int nbank;
- spinlock_t lock;
+ raw_spinlock_t lock;
struct gpio_chip chip;
struct atlas7_gpio_bank banks[0];
};
@@ -5650,13 +5650,13 @@ static void atlas7_gpio_irq_ack(struct irq_data *d)
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
/* clear interrupt status */
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
@@ -5681,11 +5681,11 @@ static void atlas7_gpio_irq_mask(struct irq_data *d)
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_irq_mask(a7gc, d->hwirq);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static void atlas7_gpio_irq_unmask(struct irq_data *d)
@@ -5701,14 +5701,14 @@ static void atlas7_gpio_irq_unmask(struct irq_data *d)
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static int atlas7_gpio_irq_type(struct irq_data *d,
@@ -5725,7 +5725,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d,
pin_in_bank = d->hwirq - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ctrl_reg);
val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
@@ -5768,7 +5768,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d,
writel(val, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5863,7 +5863,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
if (pinctrl_request_gpio(chip->base + gpio))
return -ENODEV;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
/*
* default status:
@@ -5872,7 +5872,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
__atlas7_gpio_set_input(a7gc, gpio);
__atlas7_gpio_irq_mask(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5883,12 +5883,12 @@ static void atlas7_gpio_free(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_irq_mask(a7gc, gpio);
__atlas7_gpio_set_input(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
pinctrl_free_gpio(chip->base + gpio);
}
@@ -5899,11 +5899,11 @@ static int atlas7_gpio_direction_input(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_set_input(a7gc, gpio);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5936,11 +5936,11 @@ static int atlas7_gpio_direction_output(struct gpio_chip *chip,
struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
unsigned long flags;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
__atlas7_gpio_set_output(a7gc, gpio, value);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return 0;
}
@@ -5956,11 +5956,11 @@ static int atlas7_gpio_get_value(struct gpio_chip *chip,
bank = atlas7_gpio_to_bank(a7gc, gpio);
pin_in_bank = gpio - bank->gpio_offset;
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
}
@@ -5978,7 +5978,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip,
pin_in_bank = gpio - bank->gpio_offset;
ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
- spin_lock_irqsave(&a7gc->lock, flags);
+ raw_spin_lock_irqsave(&a7gc->lock, flags);
ctrl = readl(ctrl_reg);
if (value)
@@ -5987,7 +5987,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip,
ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
writel(ctrl, ctrl_reg);
- spin_unlock_irqrestore(&a7gc->lock, flags);
+ raw_spin_unlock_irqrestore(&a7gc->lock, flags);
}
static const struct of_device_id atlas7_gpio_ids[] = {
@@ -6036,7 +6036,7 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
}
a7gc->nbank = nbank;
- spin_lock_init(&a7gc->lock);
+ raw_spin_lock_init(&a7gc->lock);
/* Setup GPIO Chip */
chip = &a7gc->chip;
--
2.11.1
next prev parent reply other threads:[~2017-03-09 17:06 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 16:21 [PATCH 00/19] fixup usage of non-raw spinlocks in irqchips Julia Cartwright
2017-03-09 16:21 ` [PATCH 01/19] Coccinelle: locks: identify callers of spin_lock{,_irq,_irqsave}() in irqchip implementations Julia Cartwright
2017-03-09 20:15 ` Julia Lawall
2017-03-09 21:37 ` Julia Cartwright
2017-03-09 16:21 ` [PATCH 02/19] gpio: altera: make use of raw_spinlock variants Julia Cartwright
2017-03-15 9:53 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 03/19] alpha: marvel: " Julia Cartwright
2017-03-12 2:58 ` kbuild test robot
2017-03-09 16:21 ` [PATCH 04/19] powerpc: mpc52xx_gpt: " Julia Cartwright
2017-03-09 16:21 ` [PATCH 05/19] gpio: 104-dio-48e: " Julia Cartwright
2017-03-09 18:35 ` William Breathitt Gray
2017-03-15 9:54 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 06/19] gpio: ath79: " Julia Cartwright
2017-03-13 19:51 ` Alban
2017-03-15 9:59 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 07/19] gpio: bcm-kona: " Julia Cartwright
2017-03-10 17:28 ` Ray Jui
2017-03-10 19:35 ` Julia Cartwright
2017-03-15 9:57 ` Linus Walleij
2017-03-15 9:56 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 08/19] gpio: etraxfs: " Julia Cartwright
2017-03-15 10:00 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 09/19] gpio: pl061: " Julia Cartwright
2017-03-15 10:01 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 10/19] gpio: ws16c48: " Julia Cartwright
2017-03-09 18:36 ` William Breathitt Gray
2017-03-15 10:02 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 11/19] gpio: zx: " Julia Cartwright
2017-03-15 10:03 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 12/19] i2c: mux: pca954x: " Julia Cartwright
2017-03-16 19:38 ` Peter Rosin
2017-03-09 16:22 ` [PATCH 13/19] mfd: asic3: " Julia Cartwright
2017-03-09 16:22 ` [PATCH 14/19] mfd: t7l66xb: " Julia Cartwright
2017-03-15 11:17 ` Lee Jones
2017-03-15 19:07 ` Julia Cartwright
2017-03-16 9:22 ` Lee Jones
2017-03-09 16:22 ` [PATCH 15/19] mfd: tc6393xb: " Julia Cartwright
2017-03-09 16:22 ` [PATCH 16/19] pinctrl: bcm: " Julia Cartwright
2017-03-15 10:11 ` Linus Walleij
2017-03-09 16:22 ` [PATCH 17/19] pinctrl: amd: " Julia Cartwright
2017-03-15 10:12 ` Linus Walleij
2017-03-09 16:22 ` Julia Cartwright [this message]
2017-03-15 10:13 ` [PATCH 18/19] pinctrl: sirf: atlas7: " Linus Walleij
2017-03-09 16:22 ` [PATCH 19/19] pinctrl: sunxi: " Julia Cartwright
2017-03-15 10:14 ` Linus Walleij
2017-03-15 9:51 ` [PATCH 00/19] fixup usage of non-raw spinlocks in irqchips Linus Walleij
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