From: Julia Cartwright <julia@ni.com>
To: Tien Hock Loh <thloh@altera.com>,
Linus Walleij <linus.walleij@linaro.org>,
Alexandre Courbot <gnurou@gmail.com>
Cc: <linux-kernel@vger.kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
<linux-gpio@vger.kernel.org>
Subject: [PATCH 02/19] gpio: altera: make use of raw_spinlock variants
Date: Thu, 9 Mar 2017 10:21:49 -0600 [thread overview]
Message-ID: <f655096ca76ca81032ab07e67412da0a116bbbb6.1489015238.git.julia@ni.com> (raw)
In-Reply-To: <cover.1489015238.git.julia@ni.com>
The altera gpio driver currently implements an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a real-time
kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT
kernels, it is not suitable to be used with irq_chips.
A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: Julia Cartwright <julia@ni.com>
---
drivers/gpio/gpio-altera.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-altera.c b/drivers/gpio/gpio-altera.c
index 3fe6a21e05a5..17485dc20384 100644
--- a/drivers/gpio/gpio-altera.c
+++ b/drivers/gpio/gpio-altera.c
@@ -38,7 +38,7 @@
*/
struct altera_gpio_chip {
struct of_mm_gpio_chip mmchip;
- spinlock_t gpio_lock;
+ raw_spinlock_t gpio_lock;
int interrupt_trigger;
int mapped_irq;
};
@@ -53,12 +53,12 @@ static void altera_gpio_irq_unmask(struct irq_data *d)
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
mm_gc = &altera_gc->mmchip;
- spin_lock_irqsave(&altera_gc->gpio_lock, flags);
+ raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
intmask |= BIT(irqd_to_hwirq(d));
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
- spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
+ raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
}
static void altera_gpio_irq_mask(struct irq_data *d)
@@ -71,12 +71,12 @@ static void altera_gpio_irq_mask(struct irq_data *d)
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
mm_gc = &altera_gc->mmchip;
- spin_lock_irqsave(&altera_gc->gpio_lock, flags);
+ raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
intmask &= ~BIT(irqd_to_hwirq(d));
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
- spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
+ raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
}
/**
@@ -140,14 +140,14 @@ static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc);
- spin_lock_irqsave(&chip->gpio_lock, flags);
+ raw_spin_lock_irqsave(&chip->gpio_lock, flags);
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
if (value)
data_reg |= BIT(offset);
else
data_reg &= ~BIT(offset);
writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
- spin_unlock_irqrestore(&chip->gpio_lock, flags);
+ raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
}
static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -160,12 +160,12 @@ static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc);
- spin_lock_irqsave(&chip->gpio_lock, flags);
+ raw_spin_lock_irqsave(&chip->gpio_lock, flags);
/* Set pin as input, assumes software controlled IP */
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
gpio_ddr &= ~BIT(offset);
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
- spin_unlock_irqrestore(&chip->gpio_lock, flags);
+ raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0;
}
@@ -181,7 +181,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc);
- spin_lock_irqsave(&chip->gpio_lock, flags);
+ raw_spin_lock_irqsave(&chip->gpio_lock, flags);
/* Sets the GPIO value */
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
if (value)
@@ -194,7 +194,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
gpio_ddr |= BIT(offset);
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
- spin_unlock_irqrestore(&chip->gpio_lock, flags);
+ raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0;
}
@@ -262,7 +262,7 @@ static int altera_gpio_probe(struct platform_device *pdev)
if (!altera_gc)
return -ENOMEM;
- spin_lock_init(&altera_gc->gpio_lock);
+ raw_spin_lock_init(&altera_gc->gpio_lock);
if (of_property_read_u32(node, "altr,ngpio", ®))
/* By default assume maximum ngpio */
--
2.11.1
next prev parent reply other threads:[~2017-03-09 17:00 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 16:21 [PATCH 00/19] fixup usage of non-raw spinlocks in irqchips Julia Cartwright
2017-03-09 16:21 ` [PATCH 01/19] Coccinelle: locks: identify callers of spin_lock{,_irq,_irqsave}() in irqchip implementations Julia Cartwright
2017-03-09 20:15 ` Julia Lawall
2017-03-09 21:37 ` Julia Cartwright
2017-03-09 16:21 ` Julia Cartwright [this message]
2017-03-15 9:53 ` [PATCH 02/19] gpio: altera: make use of raw_spinlock variants Linus Walleij
2017-03-09 16:21 ` [PATCH 03/19] alpha: marvel: " Julia Cartwright
2017-03-12 2:58 ` kbuild test robot
2017-03-09 16:21 ` [PATCH 04/19] powerpc: mpc52xx_gpt: " Julia Cartwright
2017-03-09 16:21 ` [PATCH 05/19] gpio: 104-dio-48e: " Julia Cartwright
2017-03-09 18:35 ` William Breathitt Gray
2017-03-15 9:54 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 06/19] gpio: ath79: " Julia Cartwright
2017-03-13 19:51 ` Alban
2017-03-15 9:59 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 07/19] gpio: bcm-kona: " Julia Cartwright
2017-03-10 17:28 ` Ray Jui
2017-03-10 19:35 ` Julia Cartwright
2017-03-15 9:57 ` Linus Walleij
2017-03-15 9:56 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 08/19] gpio: etraxfs: " Julia Cartwright
2017-03-15 10:00 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 09/19] gpio: pl061: " Julia Cartwright
2017-03-15 10:01 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 10/19] gpio: ws16c48: " Julia Cartwright
2017-03-09 18:36 ` William Breathitt Gray
2017-03-15 10:02 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 11/19] gpio: zx: " Julia Cartwright
2017-03-15 10:03 ` Linus Walleij
2017-03-09 16:21 ` [PATCH 12/19] i2c: mux: pca954x: " Julia Cartwright
2017-03-16 19:38 ` Peter Rosin
2017-03-09 16:22 ` [PATCH 13/19] mfd: asic3: " Julia Cartwright
2017-03-09 16:22 ` [PATCH 14/19] mfd: t7l66xb: " Julia Cartwright
2017-03-15 11:17 ` Lee Jones
2017-03-15 19:07 ` Julia Cartwright
2017-03-16 9:22 ` Lee Jones
2017-03-09 16:22 ` [PATCH 15/19] mfd: tc6393xb: " Julia Cartwright
2017-03-09 16:22 ` [PATCH 16/19] pinctrl: bcm: " Julia Cartwright
2017-03-15 10:11 ` Linus Walleij
2017-03-09 16:22 ` [PATCH 17/19] pinctrl: amd: " Julia Cartwright
2017-03-15 10:12 ` Linus Walleij
2017-03-09 16:22 ` [PATCH 18/19] pinctrl: sirf: atlas7: " Julia Cartwright
2017-03-15 10:13 ` Linus Walleij
2017-03-09 16:22 ` [PATCH 19/19] pinctrl: sunxi: " Julia Cartwright
2017-03-15 10:14 ` Linus Walleij
2017-03-15 9:51 ` [PATCH 00/19] fixup usage of non-raw spinlocks in irqchips Linus Walleij
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