Re: [PATCH v6 5/8] KVM: x86/pmu: Support PERF_METRICS MSR in mediated vPMU

["Chen, Zide" <zide.chen@intel.com>]

On 7/26/2026 10:49 AM, Jim Mattson wrote:
> On Mon, Jun 29, 2026 at 4:28 PM Zide Chen <zide.chen@intel.com> wrote:
>>
>> From: Dapeng Mi <dapeng1.mi@linux.intel.com>
>>
>> Bit 15 in IA32_PERF_CAPABILITIES indicates that the CPU provides
>> built-in support for Topdown Microarchitecture Analysis (TMA) L1
>> metrics via the IA32_PERF_METRICS MSR.
>>
>> Expose this capability only when mediated vPMU is enabled, as emulating
>> IA32_PERF_METRICS in the legacy vPMU model is impractical.
>>
>> Pass IA32_PERF_METRICS through to the guest only when mediated vPMU is
>> enabled and bit 15 is set in guest IA32_PERF_CAPABILITIES.  Allow
>> kvm_pmu_{get,set}_msr() to handle this MSR for host accesses.
>>
>> Save and restore this MSR on host/guest PMU context switches so that
>> host PMU activity does not clobber the guest value, and guest state
>> is not leaked into the host.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
>> ---
>> v5:
>> - Remove host_initiated check in set/get MSR handlers.
>> v4:
>> - Remove WARN_ON_ONCE() and simply reject the guest accesses by checking
>>   host_initiated. (Sashiko)
>> - Passthru MSR_PERF_METRICS only if has_mediated_pmu is true. (Sashiko)
>> - Remove the redundant !! in vcpu_has_perf_metrics().
>> v3:
>> - Replace WARN_ON() with WARN_ON_ONCE(). (Dapeng)
>> - Add comments to explain why we don't validate writes on PERF_METRICS.
>> ---
>>  arch/x86/include/asm/kvm_host.h   |  1 +
>>  arch/x86/include/asm/msr-index.h  |  1 +
>>  arch/x86/include/asm/perf_event.h |  1 +
>>  arch/x86/kvm/msrs.c               |  6 +++++-
>>  arch/x86/kvm/pmu.h                |  5 +++++
>>  arch/x86/kvm/vmx/pmu_intel.c      | 31 +++++++++++++++++++++++++++++++
>>  arch/x86/kvm/vmx/vmx.c            |  7 +++++++
>>  7 files changed, 51 insertions(+), 1 deletion(-)
>>
>> ...
>> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>> index b736b9ff965b..21eb4b339fa6 100644
>> --- a/arch/x86/kvm/vmx/vmx.c
>> +++ b/arch/x86/kvm/vmx/vmx.c
>> @@ -4273,6 +4273,10 @@ static void vmx_recalc_pmu_msr_intercepts(struct kvm_vcpu *vcpu)
>>                                   MSR_TYPE_RW, intercept);
>>         vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>>                                   MSR_TYPE_RW, intercept);
>> +
>> +       intercept = !has_mediated_pmu || !kvm_vcpu_has_perf_metrics(vcpu);
>> +       vmx_set_intercept_for_msr(vcpu, MSR_PERF_METRICS,
>> +                                 MSR_TYPE_RW, intercept);
>>  }
> 
> Should we also update nested_vmx_merge_pmu_msr_bitmaps()?

Yes, I can include nested_vmx_merge_pmu_msr_bitmaps() in v7 and post it
today.

I just verified that Topdown works correctly, including MSR passthrough
and RDPMC passthrough in a nested Linux setup on top of the vPMU v5
series (to enable medisted vPMU on nested).

Initially, I was planning to revisit this as part of a broader effort on
nested PMU virtualization, including features such as Arch LBR. However,
I now agree that including it in this series makes sense.