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* [PATCH] mmc: sdhci-brcmstb: use correct register offset for V1 pin_sel restore
@ 2026-02-16 19:15 Kamal Dasu
  2026-02-17 14:55 ` Ulf Hansson
  2026-02-17 18:47 ` Florian Fainelli
  0 siblings, 2 replies; 4+ messages in thread
From: Kamal Dasu @ 2026-02-16 19:15 UTC (permalink / raw)
  To: adrian.hunter, ulf.hansson, florian.fainelli
  Cc: bcm-kernel-feedback-list, linux-mmc, linux-arm-kernel,
	linux-kernel, Kamal Dasu

The restore path for SDIO_CFG_CORE_V1 was incorrectly using
SDIO_CFG_SD_PIN_SEL (offset 0x44) instead of SDIO_CFG_V1_SD_PIN_SEL
(offset 0x54), causing the wrong register to be written on resume.
The save path already uses the correct V1-specific offset. This
affects BCM7445 and BCM72116 platforms which use the V1 config core.

Fixes: b7e614802e3f ("mmc: sdhci-brcmstb: save and restore registers during PM")
Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
---
 drivers/mmc/host/sdhci-brcmstb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index c9442499876c..57e45951644e 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -116,7 +116,7 @@ static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver v
 		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
 
 	if (ver == SDIO_CFG_CORE_V1) {
-		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+		writel(sr->sd_pin_sel, cr + SDIO_CFG_V1_SD_PIN_SEL);
 		return;
 	}
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2026-02-18 11:29 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-02-16 19:15 [PATCH] mmc: sdhci-brcmstb: use correct register offset for V1 pin_sel restore Kamal Dasu
2026-02-17 14:55 ` Ulf Hansson
2026-02-17 18:47 ` Florian Fainelli
2026-02-18 11:28   ` Ulf Hansson

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