[PATCH 0/2] k3-am62p: Add MCU SRAM node and Reserve RTOS IPC memory

[PATCH 0/2] k3-am62p: Add MCU SRAM node and Reserve RTOS IPC memory

[Sai Sree Kartheek Adivi]

The first patch adds MCU SRAM node to the device tree. The second
patch reserves shared memory for RTOS IPC communications and makes
the MCU SRAM accessible to R5 remote proc driver for image loading.

Hari Nagalla (2):
  arm64: dts: ti: k3-am62p: Add MCU SRAM node
  arm64: dts: ti: k3-am62p-ti-ipc-firmware: Reserve RTOS IPC memory

 .../arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 12 ++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi |  7 +++++++
 2 files changed, 19 insertions(+)

-- 
2.54.0

[PATCH 1/2] arm64: dts: ti: k3-am62p: Add MCU SRAM node

[Sai Sree Kartheek Adivi]

From: Hari Nagalla <hnagalla@ti.com>

AM62P devices have two banks of 256KB each SRAM in MCU domain. This
memory is typically used by MCU R5 firmware for low latency accesses.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
 .../arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index 2394a4fb5a94c..278404cadcd98 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -6,6 +6,18 @@
  */
 
 &cbass_mcu {
+	mcu_ram: sram@79100000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x79100000 0x00 0x80000>;
+		ranges = <0x00 0x00 0x79100000 0x80000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mcu1-sram@0 {
+			reg = <0x0 0x80000>;
+		};
+	};
+
 	mcu_pmx0: pinctrl@4084000 {
 		compatible = "pinctrl-single";
 		reg = <0x00 0x04084000 0x00 0x88>;
-- 
2.54.0

[PATCH 2/2] arm64: dts: ti: k3-am62p-ti-ipc-firmware: Reserve RTOS IPC memory

[Sai Sree Kartheek Adivi]

From: Hari Nagalla <hnagalla@ti.com>

TI IPC firmware uses RTOS-RTOS between Wakeup R5 and MCU R5. This IPC
needs shared memory buffers. Reserve memory to facilitate this IPC.

In addition TI MCU R5 firmware also uses MCU SRAM, hence make this
SRAM accessible to R5 remote proc for image loading.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
index 5d7f701420e2d..7084d85665f4d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
@@ -6,6 +6,12 @@
  */
 
 &reserved_memory {
+	rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0x9b500000 0x00 0x00300000>;
+		no-map;
+	};
+
 	mcu_r5fss0_core0_dma_memory_region: memory@9b800000 {
 		compatible = "shared-dma-pool";
 		reg = <0x00 0x9b800000 0x00 0x100000>;
@@ -54,6 +60,7 @@ &mcu_r5fss0 {
 };
 
 &mcu_r5fss0_core0 {
+	sram = <&mcu_ram>;
 	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 			<&mcu_r5fss0_core0_memory_region>;
-- 
2.54.0

Re: [PATCH 1/2] arm64: dts: ti: k3-am62p: Add MCU SRAM node

[Kumar, Udit]

On 9/28/2026 8:52 AM, Sai Sree Kartheek Adivi wrote:
> From: Hari Nagalla <hnagalla@ti.com>
> 
> AM62P devices have two banks of 256KB each SRAM in MCU domain. This
> memory is typically used by MCU R5 firmware for low latency accesses.
> 

> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> Signed-off-by: Judith Mendez <jm@ti.com>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
> ---
>  .../arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> index 2394a4fb5a94c..278404cadcd98 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> @@ -6,6 +6,18 @@
>   */
>  
>  &cbass_mcu {
> +	mcu_ram: sram@79100000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00 0x79100000 0x00 0x80000>;
> +		ranges = <0x00 0x00 0x79100000 0x80000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +

commit message says, 2 banks of 256Kb, Here you have only 1 block.
Please add description, why you are adding 1 block only

> +		mcu1-sram@0 {
> +			reg = <0x0 0x80000>;
> +		};

what is use of this ?,

If you really need this then, please make it block of 256Kb (something
like below)

mcu-sram-0 {
 			reg = <0x0 0x40000>;
 		};

mcu-sram-1 {
			reg = <0x40000 0x40000>;
		};


> +	};
> +
>  	mcu_pmx0: pinctrl@4084000 {
>  		compatible = "pinctrl-single";
>  		reg = <0x00 0x04084000 0x00 0x88>;