* [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx
@ 2026-01-12 23:20 Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
` (11 more replies)
0 siblings, 12 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
The Samsung HDMI/eDP Transmitter Combo PHY is capable of handling four
HDMI 2.1 Fixed Rate Link (FRL) lanes, while each lane can operate at
3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps.
This patchset extends the HDMI PHY configuration API to manage the FRL
mode and provides all the required HDMI driver changes to enable FRL in
addition to the already supported TMDS mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Changes in v6:
- Rebased series onto next-20260109 and removed all patch dependencies
- Handled the conflicts caused by the recent conversion from
round_rate() to determine_rate()
- Link to v5: https://lore.kernel.org/r/20251221-phy-hdptx-frl-v5-0-dac390a780be@collabora.com
Changes in v5:
- Dropped all unused members from struct lcpll_config and improved the
readability of the rk_hdptx_frl_lcpll_cfg table
- Rebased series onto v6.19-rc1 and replaced dependency [1] with [2]
(the former got merged)
- Link to v4: https://lore.kernel.org/r/20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com
Changes in v4:
- Moved the following fixup patches into a separate series [1]:
* Fix reported clock rate in high bpc mode
* Reduce ROPLL loop bandwidth
* Prevent Inter-Pair Skew from exceeding the limits
- Renamed enum phy_mode_hdmi to phy_hdmi_mode and
PHY_MODE_HDMI_{TMDS|FRL} to PHY_HDMI_MODE_{TMDS|FRL} (Dmitry)
- Rebased remaining patches onto next-20250901
- Link to v3: https://lore.kernel.org/r/20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com
Changes in v3:
- Reworked patch "phy: hdmi: Add HDMI 2.1 FRL configuration options"
according to Dmitry's feedback
* Updated commit message providing a brief description of FRL mode
* Kept PHY_MODE_HDMI in enum phy_mode and introduced enum
phy_mode_hdmi defining the TMDS and FRL submodes
- Updated "phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support"
* Implemented .set_mode() callback in rk_hdptx_phy_ops
* Introduced .mode member in struct rk_hdptx_hdmi_cfg and used it
instead of phy_get_mode() to verify PHY_MODE_HDMI_FRL
- Rebased series onto next-20250818
- Link to v2: https://lore.kernel.org/r/20250805-phy-hdptx-frl-v2-0-d118bd4b6e0b@collabora.com
Changes in v2:
- Added a couple of new patches:
* Fix reported clock rate in high bpc mode
* Drop hw_rate driver data
- Applied several tweaks to the following patches:
* Compute clk rate from PLL config
* Switch to driver specific HDMI config
* Add HDMI 2.1 FRL support
- Rebased series onto next-20250804
- Link to v1: https://lore.kernel.org/r/20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com
---
Cristian Ciocaltea (11):
phy: hdmi: Add HDMI 2.1 FRL configuration options
phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()
phy: rockchip: samsung-hdptx: Fix coding style alignment
phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
phy: rockchip: samsung-hdptx: Enable lane output in common helper
phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
phy: rockchip: samsung-hdptx: Drop hw_rate driver data
phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 667 ++++++++++++++++++----
include/linux/phy/phy-hdmi.h | 19 +-
2 files changed, 585 insertions(+), 101 deletions(-)
---
base-commit: f417b7ffcbef7d76b0d8860518f50dae0e7e5eda
change-id: 20250708-phy-hdptx-frl-fc3377db9f2e
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
The HDMI 2.1 specification introduced the Fixed Rate Link (FRL) mode,
aiming to replace the older Transition-Minimized Differential Signaling
(TMDS) mode used in previous HDMI versions to support much higher
bandwidths (up to 48 Gbps) for modern video and audio formats.
FRL has been designed to support ultra high resolution formats at high
refresh rates like 8K@60Hz or 4K@120Hz, and eliminates the need for
dynamic bandwidth adjustments, which reduces latency. It operates with
3 or 4 lanes at different link rates: 3Gbps, 6Gbps, 8Gbps, 10Gbps or
12Gbps.
Add support for configuring the FRL mode for HDMI PHYs.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
index f0ec963c6e84..d4cf4430ee8f 100644
--- a/include/linux/phy/phy-hdmi.h
+++ b/include/linux/phy/phy-hdmi.h
@@ -6,16 +6,31 @@
#ifndef __PHY_HDMI_H_
#define __PHY_HDMI_H_
+#include <linux/types.h>
+
+enum phy_hdmi_mode {
+ PHY_HDMI_MODE_TMDS,
+ PHY_HDMI_MODE_FRL,
+};
+
/**
* struct phy_configure_opts_hdmi - HDMI configuration set
- * @tmds_char_rate: HDMI TMDS Character Rate in Hertz.
* @bpc: Bits per color channel.
+ * @tmds_char_rate: HDMI TMDS Character Rate in Hertz.
+ * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps.
+ * @frl.lanes: HDMI FRL lanes count.
*
* This structure is used to represent the configuration state of a HDMI phy.
*/
struct phy_configure_opts_hdmi {
- unsigned long long tmds_char_rate;
unsigned int bpc;
+ union {
+ unsigned long long tmds_char_rate;
+ struct {
+ u8 rate_per_lane;
+ u8 lanes;
+ } frl;
+ };
};
#endif /* __PHY_HDMI_H_ */
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-13 8:13 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
` (9 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
rk_hdptx_dp_reset() is allowed to sleep, hence replace the busy waiting
with usleep_range(), to allow other threads to run.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index a65e96694237..89710066d70c 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1042,7 +1042,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
reset_control_assert(hdptx->rsts[RST_APB].rstc);
- udelay(10);
+ usleep_range(10, 15);
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
regmap_update_bits(hdptx->regmap, LANE_REG(0301),
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-13 8:11 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
` (8 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
Handle a bunch of reported checkpatch.pl complaints:
CHECK: Alignment should match open parenthesis
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 89710066d70c..3f8a7f4f5cd8 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
LN_TX_JEQ_ODD_CTRL_RBR_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_RBR_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
@@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
LN_TX_JEQ_ODD_CTRL_HBR_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_HBR_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
@@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_HBR2_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (2 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-13 8:12 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
` (7 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
Fix the naming inconsistencies for some of the functions and global
variables:
* Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable
* Replace '_ropll_tmds_' with '_tmds_ropll_' globally
* Replace 'hdtpx' with 'hdptx' globally
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 62 +++++++++++------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3f8a7f4f5cd8..3c6eb6dbadd0 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -32,17 +32,17 @@
#define HDPTX_O_PHY_RDY BIT(1)
#define HDPTX_O_SB_RDY BIT(0)
-#define HDTPX_REG(_n, _min, _max) \
+#define HDPTX_REG(_n, _min, _max) \
( \
BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
((0x##_n) * 4) \
)
-#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
-#define SB_REG(n) HDTPX_REG(n, 0100, 0129)
-#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
-#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
+#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7)
+#define SB_REG(n) HDPTX_REG(n, 0100, 0129)
+#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229)
+#define LANE_REG(n) HDPTX_REG(n, 0300, 062d)
/* CMN_REG(0008) */
#define OVRD_LCPLL_EN_MASK BIT(7)
@@ -397,7 +397,7 @@ struct rk_hdptx_phy {
unsigned int lanes;
};
-static const struct ropll_config ropll_tmds_cfg[] = {
+static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
/* | pms | sdm | sdc | */
/* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, num, deno, */
{ 594000000ULL, 124, 124, 1, 1, 0, 1, 62, 1, 16, 5, 0, 1, },
@@ -424,7 +424,7 @@ static const struct ropll_config ropll_tmds_cfg[] = {
{ 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, 1, 1, },
};
-static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
+static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0009), 0x0c),
REG_SEQ0(CMN_REG(000a), 0x83),
REG_SEQ0(CMN_REG(000b), 0x06),
@@ -514,7 +514,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(009b), 0x10),
};
-static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
+static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0008), 0x00),
REG_SEQ0(CMN_REG(0011), 0x01),
REG_SEQ0(CMN_REG(0017), 0x20),
@@ -556,14 +556,14 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(009b), 0x00),
};
-static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
+static const struct reg_sequence rk_hdptx_common_sb_init_seq[] = {
REG_SEQ0(SB_REG(0114), 0x00),
REG_SEQ0(SB_REG(0115), 0x00),
REG_SEQ0(SB_REG(0116), 0x00),
REG_SEQ0(SB_REG(0117), 0x00),
};
-static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
+static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] = {
REG_SEQ0(LNTOP_REG(0201), 0x00),
REG_SEQ0(LNTOP_REG(0202), 0x00),
REG_SEQ0(LNTOP_REG(0203), 0x0f),
@@ -571,7 +571,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
REG_SEQ0(LNTOP_REG(0205), 0xff),
};
-static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
+static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] = {
REG_SEQ0(LNTOP_REG(0201), 0x07),
REG_SEQ0(LNTOP_REG(0202), 0xc1),
REG_SEQ0(LNTOP_REG(0203), 0xf0),
@@ -579,7 +579,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
REG_SEQ0(LNTOP_REG(0205), 0x1f),
};
-static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
+static const struct reg_sequence rk_hdptx_common_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0303), 0x0c),
REG_SEQ0(LANE_REG(0307), 0x20),
REG_SEQ0(LANE_REG(030a), 0x17),
@@ -634,7 +634,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0620), 0xa0),
};
-static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
+static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0312), 0x00),
REG_SEQ0(LANE_REG(0412), 0x00),
REG_SEQ0(LANE_REG(0512), 0x00),
@@ -938,7 +938,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
return true;
}
-static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
+static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
{
const struct ropll_config *cfg = NULL;
struct ropll_config rc = {0};
@@ -947,9 +947,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
if (!hdptx->hdmi_cfg.tmds_char_rate)
return 0;
- for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
- if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
- cfg = &ropll_tmds_cfg[i];
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
+ if (hdptx->hdmi_cfg.tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
+ cfg = &rk_hdptx_tmds_ropll_cfg[i];
break;
}
@@ -969,8 +969,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
rk_hdptx_pre_power_up(hdptx);
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq);
regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
@@ -1012,25 +1012,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
return ret;
}
-static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
+static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
{
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
/* For 1/40 bitrate clk */
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq);
} else {
/* For 1/10 bitrate clk */
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq);
}
regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
- rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
return rk_hdptx_post_enable_lane(hdptx);
}
@@ -1089,7 +1089,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
if (mode == PHY_MODE_DP) {
rk_hdptx_dp_reset(hdptx);
} else {
- ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
+ ret = rk_hdptx_tmds_ropll_cmn_config(hdptx);
if (ret)
goto dec_usage;
}
@@ -1436,7 +1436,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
- ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
+ ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
if (ret)
rk_hdptx_phy_consumer_put(hdptx, true);
}
@@ -1459,11 +1459,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
return -EINVAL;
- for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
- if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate)
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
+ if (hdmi->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
break;
- if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
+ if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
!rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
return -EINVAL;
@@ -1891,7 +1891,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
* while the latter being executed only once, i.e. when clock remains
* in the prepared state during rate changes.
*/
- return rk_hdptx_ropll_tmds_cmn_config(hdptx);
+ return rk_hdptx_tmds_ropll_cmn_config(hdptx);
}
static const struct clk_ops hdptx_phy_clk_ops = {
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (3 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
In preparation to support FRL mode, move the PHY lane output enablement
from the TMDS specific configuration to the common *_post_enable_lane()
helper and make sure it gets turned off in *_phy_disable().
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3c6eb6dbadd0..33ebe63cdf1e 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -797,6 +797,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
(val & HDPTX_O_PHY_RDY) &&
(val & HDPTX_O_PLL_LOCK_DONE),
@@ -850,6 +852,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
usleep_range(20, 30);
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0);
regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
@@ -1027,7 +1030,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
}
regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
- regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (4 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
Drop redundant reg_sequence entries from rk_hdptx_common_cmn_init_seq[],
i.e. those that are either duplicated or overridden in
rk_hdptx_tmds_cmn_init_seq[].
Additionally, a few items do not really belong to the former, hence move
them to the latter. That's mostly a preparatory step for adding FRL
support.
No functional changes intended at this point.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 22 ++++------------------
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 33ebe63cdf1e..0a0e38e95a37 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -433,13 +433,11 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(000e), 0x0f),
REG_SEQ0(CMN_REG(000f), 0x0f),
REG_SEQ0(CMN_REG(0010), 0x04),
- REG_SEQ0(CMN_REG(0011), 0x00),
REG_SEQ0(CMN_REG(0012), 0x26),
REG_SEQ0(CMN_REG(0013), 0x22),
REG_SEQ0(CMN_REG(0014), 0x24),
REG_SEQ0(CMN_REG(0015), 0x77),
REG_SEQ0(CMN_REG(0016), 0x08),
- REG_SEQ0(CMN_REG(0017), 0x00),
REG_SEQ0(CMN_REG(0018), 0x04),
REG_SEQ0(CMN_REG(0019), 0x48),
REG_SEQ0(CMN_REG(001a), 0x01),
@@ -447,13 +445,7 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(001c), 0x01),
REG_SEQ0(CMN_REG(001d), 0x64),
REG_SEQ0(CMN_REG(001f), 0x00),
- REG_SEQ0(CMN_REG(0026), 0x53),
REG_SEQ0(CMN_REG(0029), 0x01),
- REG_SEQ0(CMN_REG(0030), 0x00),
- REG_SEQ0(CMN_REG(0031), 0x20),
- REG_SEQ0(CMN_REG(0032), 0x30),
- REG_SEQ0(CMN_REG(0033), 0x0b),
- REG_SEQ0(CMN_REG(0034), 0x23),
REG_SEQ0(CMN_REG(0035), 0x00),
REG_SEQ0(CMN_REG(0038), 0x00),
REG_SEQ0(CMN_REG(0039), 0x00),
@@ -464,7 +456,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(003f), 0x83),
REG_SEQ0(CMN_REG(0040), 0x06),
REG_SEQ0(CMN_REG(0041), 0x20),
- REG_SEQ0(CMN_REG(0042), 0xb8),
REG_SEQ0(CMN_REG(0043), 0x00),
REG_SEQ0(CMN_REG(0044), 0x46),
REG_SEQ0(CMN_REG(0045), 0x24),
@@ -474,14 +465,9 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(004b), 0x00),
REG_SEQ0(CMN_REG(004c), 0x01),
REG_SEQ0(CMN_REG(004d), 0x64),
- REG_SEQ0(CMN_REG(004e), 0x14),
REG_SEQ0(CMN_REG(004f), 0x00),
REG_SEQ0(CMN_REG(0050), 0x00),
- REG_SEQ0(CMN_REG(005d), 0x0c),
REG_SEQ0(CMN_REG(005f), 0x01),
- REG_SEQ0(CMN_REG(006b), 0x04),
- REG_SEQ0(CMN_REG(0073), 0x30),
- REG_SEQ0(CMN_REG(0074), 0x00),
REG_SEQ0(CMN_REG(0075), 0x20),
REG_SEQ0(CMN_REG(0076), 0x30),
REG_SEQ0(CMN_REG(0077), 0x08),
@@ -493,13 +479,10 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(007e), 0x00),
REG_SEQ0(CMN_REG(007f), 0x00),
REG_SEQ0(CMN_REG(0080), 0x00),
- REG_SEQ0(CMN_REG(0081), 0x09),
REG_SEQ0(CMN_REG(0082), 0x04),
REG_SEQ0(CMN_REG(0083), 0x24),
REG_SEQ0(CMN_REG(0084), 0x20),
REG_SEQ0(CMN_REG(0085), 0x03),
- REG_SEQ0(CMN_REG(0086), 0x01),
- REG_SEQ0(CMN_REG(0087), 0x0c),
REG_SEQ0(CMN_REG(008a), 0x55),
REG_SEQ0(CMN_REG(008b), 0x25),
REG_SEQ0(CMN_REG(008c), 0x2c),
@@ -511,7 +494,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0092), 0x00),
REG_SEQ0(CMN_REG(0093), 0x00),
REG_SEQ0(CMN_REG(009a), 0x11),
- REG_SEQ0(CMN_REG(009b), 0x10),
};
static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
@@ -545,9 +527,13 @@ static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0048), 0x11),
REG_SEQ0(CMN_REG(004e), 0x34),
REG_SEQ0(CMN_REG(005c), 0x25),
+ REG_SEQ0(CMN_REG(005d), 0x0c),
REG_SEQ0(CMN_REG(005e), 0x4f),
+ REG_SEQ0(CMN_REG(006b), 0x04),
+ REG_SEQ0(CMN_REG(0073), 0x30),
REG_SEQ0(CMN_REG(0074), 0x04),
REG_SEQ0(CMN_REG(0081), 0x01),
+ REG_SEQ0(CMN_REG(0086), 0x01),
REG_SEQ0(CMN_REG(0087), 0x04),
REG_SEQ0(CMN_REG(0089), 0x00),
REG_SEQ0(CMN_REG(0095), 0x00),
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (5 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the
initial clock rate based on the actual PHY PLL configuration as
retrieved from the related hardware registers.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 91 ++++++++++++++++++++++-
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 0a0e38e95a37..3cc8976e10e6 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1818,12 +1818,101 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
rk_hdptx_phy_consumer_put(hdptx, true);
}
+#define PLL_REF_CLK 24000000ULL
+
+static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx)
+{
+ struct ropll_config ropll_hw;
+ u64 fout, sdm;
+ u32 mode, val;
+ int ret;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0008), &mode);
+ if (ret)
+ return 0;
+
+ if (mode & LCPLL_LCVCO_MODE_EN_MASK)
+ return 0;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0051), &val);
+ if (ret)
+ return 0;
+ ropll_hw.pms_mdiv = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(005E), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdm_en = val & ROPLL_SDM_EN_MASK;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0064), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdm_num_sign = val & ROPLL_SDM_NUM_SIGN_RBR_MASK;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0065), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdm_num = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0060), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdm_deno = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0069), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdc_n = (val & ROPLL_SDC_N_RBR_MASK) + 3;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(006c), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdc_num = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0070), &val);
+ if (ret)
+ return 0;
+ ropll_hw.sdc_deno = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0086), &val);
+ if (ret)
+ return 0;
+ ropll_hw.pms_sdiv = ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1;
+
+ fout = PLL_REF_CLK * ropll_hw.pms_mdiv;
+ if (ropll_hw.sdm_en) {
+ sdm = div_u64(PLL_REF_CLK * ropll_hw.sdc_deno *
+ ropll_hw.pms_mdiv * ropll_hw.sdm_num,
+ 16 * ropll_hw.sdm_deno *
+ (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num));
+
+ if (ropll_hw.sdm_num_sign)
+ fout = fout - sdm;
+ else
+ fout = fout + sdm;
+ }
+
+ return div_u64(fout * 2, ropll_hw.pms_sdiv * 10);
+}
+
static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+ u32 status;
+ u64 rate;
+ int ret;
+
+ if (hdptx->hw_rate)
+ return hdptx->hw_rate;
+
+ ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status);
+ if (ret || !(status & HDPTX_I_PLL_EN))
+ return 0;
+
+ rate = rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx);
- return hdptx->hw_rate;
+ return DIV_ROUND_CLOSEST_ULL(rate * 8, hdptx->hdmi_cfg.bpc);
}
static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (6 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep
track of the clock rate programmed in hardware and support implementing
the ->recalc_rate() callback in hdptx_phy_clk_ops.
Computing the clock rate from the actual PHY PLL configuration seems to
work reliably, hence remove the now redundant struct member.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3cc8976e10e6..6297a5171e78 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -387,7 +387,6 @@ struct rk_hdptx_phy {
/* clk provider */
struct clk_hw hw;
- unsigned long hw_rate;
bool restrict_rate_change;
atomic_t usage_count;
@@ -931,7 +930,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
{
const struct ropll_config *cfg = NULL;
struct ropll_config rc = {0};
- int ret, i;
+ int i;
if (!hdptx->hdmi_cfg.tmds_char_rate)
return 0;
@@ -993,12 +992,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,
FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));
- ret = rk_hdptx_post_enable_pll(hdptx);
- if (!ret)
- hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
- hdptx->hdmi_cfg.bpc);
-
- return ret;
+ return rk_hdptx_post_enable_pll(hdptx);
}
static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
@@ -1903,9 +1897,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
u64 rate;
int ret;
- if (hdptx->hw_rate)
- return hdptx->hw_rate;
-
ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status);
if (ret || !(status & HDPTX_I_PLL_EN))
return 0;
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (7 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
In preparation to support the FRL operation mode which gets configured
via the lanes and rate per lane tuple, switch to a driver specific
struct for configuring the link rate and bpc.
This simplifies and optimizes the implementation by allowing implicit
switches between TMDS and FRL rates, without requiring additional checks
of the active PHY mode followed by recalculations of the link rate when
operating in FRL mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 47 +++++++++++++----------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 6297a5171e78..f1cad0264952 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -373,6 +373,11 @@ struct rk_hdptx_phy_cfg {
unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
};
+struct rk_hdptx_hdmi_cfg {
+ unsigned long long rate;
+ unsigned int bpc;
+};
+
struct rk_hdptx_phy {
struct device *dev;
struct regmap *regmap;
@@ -380,7 +385,7 @@ struct rk_hdptx_phy {
int phy_id;
struct phy *phy;
- struct phy_configure_opts_hdmi hdmi_cfg;
+ struct rk_hdptx_hdmi_cfg hdmi_cfg;
struct clk_bulk_data *clks;
int nr_clks;
struct reset_control_bulk_data rsts[RST_MAX];
@@ -932,19 +937,19 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
struct ropll_config rc = {0};
int i;
- if (!hdptx->hdmi_cfg.tmds_char_rate)
+ if (!hdptx->hdmi_cfg.rate)
return 0;
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
- if (hdptx->hdmi_cfg.tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
+ if (hdptx->hdmi_cfg.rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
cfg = &rk_hdptx_tmds_ropll_cfg[i];
break;
}
if (!cfg) {
- if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) {
+ if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.rate, &rc)) {
dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n",
- __func__, hdptx->hdmi_cfg.tmds_char_rate);
+ __func__, hdptx->hdmi_cfg.rate);
return -EINVAL;
}
@@ -952,7 +957,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
}
dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n",
- __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1,
+ __func__, hdptx->hdmi_cfg.rate, cfg->pms_mdiv, cfg->pms_sdiv + 1,
cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
rk_hdptx_pre_power_up(hdptx);
@@ -1001,7 +1006,7 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
- if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
+ if (hdptx->hdmi_cfg.rate > HDMI14_MAX_RATE) {
/* For 1/40 bitrate clk */
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq);
} else {
@@ -1372,19 +1377,19 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
int ret, lane;
if (mode != PHY_MODE_DP) {
- if (!hdptx->hdmi_cfg.tmds_char_rate) {
+ if (!hdptx->hdmi_cfg.rate) {
/*
* FIXME: Temporary workaround to setup TMDS char rate
* from the RK DW HDMI QP bridge driver.
* Will be removed as soon the switch to the HDMI PHY
* configuration API has been completed on both ends.
*/
- hdptx->hdmi_cfg.tmds_char_rate = phy_get_bus_width(hdptx->phy) & 0xfffffff;
- hdptx->hdmi_cfg.tmds_char_rate *= 100;
+ hdptx->hdmi_cfg.rate = phy_get_bus_width(hdptx->phy) & 0xfffffff;
+ hdptx->hdmi_cfg.rate *= 100;
}
dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
- hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc);
+ hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
}
ret = rk_hdptx_phy_consumer_get(hdptx);
@@ -1731,12 +1736,13 @@ static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opt
if (ret) {
dev_err(hdptx->dev, "invalid hdmi params for phy configure\n");
} else {
- hdptx->hdmi_cfg = opts->hdmi;
+ hdptx->hdmi_cfg.rate = opts->hdmi.tmds_char_rate;
+ hdptx->hdmi_cfg.bpc = opts->hdmi.bpc;
hdptx->restrict_rate_change = true;
}
dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
- hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc);
+ hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
return ret;
}
@@ -1916,7 +1922,7 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
* To be dropped as soon as the RK DW HDMI QP bridge driver
* switches to make use of phy_configure().
*/
- if (!hdptx->restrict_rate_change && req->rate != hdptx->hdmi_cfg.tmds_char_rate) {
+ if (!hdptx->restrict_rate_change && req->rate != hdptx->hdmi_cfg.rate) {
struct phy_configure_opts_hdmi hdmi = {
.tmds_char_rate = req->rate,
};
@@ -1925,7 +1931,7 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
if (ret)
return ret;
- hdptx->hdmi_cfg = hdmi;
+ hdptx->hdmi_cfg.rate = req->rate;
}
/*
@@ -1933,8 +1939,7 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
* hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with
* a different rate argument.
*/
- req->rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
- hdptx->hdmi_cfg.bpc);
+ req->rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.rate * 8, hdptx->hdmi_cfg.bpc);
return 0;
}
@@ -1945,11 +1950,11 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
- /* Revert any unlikely TMDS char rate change since round_rate() */
- if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) {
+ /* Revert any unlikely TMDS char rate change since determine_rate() */
+ if (hdptx->hdmi_cfg.rate != tmds_rate) {
dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
- tmds_rate, hdptx->hdmi_cfg.tmds_char_rate);
- hdptx->hdmi_cfg.tmds_char_rate = tmds_rate;
+ tmds_rate, hdptx->hdmi_cfg.rate);
+ hdptx->hdmi_cfg.rate = tmds_rate;
}
/*
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (8 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
2026-01-21 8:52 ` [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Vinod Koul
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
In order to facilitate introduction of HDMI 2.1 FRL support and to avoid
recomputing the link rate after verifying the HDMI configuration given
as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an
optional output parameter to store the validated configuration.
For improved code readability, also rename the existing hdmi input
parameter.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 35 ++++++++++++-----------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index f1cad0264952..c9942aaf2766 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1439,25 +1439,24 @@ static int rk_hdptx_phy_power_off(struct phy *phy)
}
static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
- struct phy_configure_opts_hdmi *hdmi)
+ struct phy_configure_opts_hdmi *hdmi_in,
+ struct rk_hdptx_hdmi_cfg *hdmi_out)
{
int i;
- if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
+ if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
- if (hdmi->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
+ if (hdmi_in->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
break;
if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
- !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
+ !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL))
return -EINVAL;
- if (!hdmi->bpc)
- hdmi->bpc = 8;
-
- switch (hdmi->bpc) {
+ switch (hdmi_in->bpc) {
+ case 0:
case 8:
case 10:
case 12:
@@ -1467,6 +1466,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
return -EINVAL;
}
+ if (hdmi_out) {
+ hdmi_out->rate = hdmi_in->tmds_char_rate;
+ hdmi_out->bpc = hdmi_in->bpc ?: 8;
+ }
+
return 0;
}
@@ -1732,17 +1736,15 @@ static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opt
int ret;
if (mode != PHY_MODE_DP) {
- ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi);
+ ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, &hdptx->hdmi_cfg);
if (ret) {
dev_err(hdptx->dev, "invalid hdmi params for phy configure\n");
} else {
- hdptx->hdmi_cfg.rate = opts->hdmi.tmds_char_rate;
- hdptx->hdmi_cfg.bpc = opts->hdmi.bpc;
hdptx->restrict_rate_change = true;
+ dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
+ hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
}
- dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
- hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
return ret;
}
@@ -1786,7 +1788,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode,
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
if (mode != PHY_MODE_DP)
- return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi);
+ return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, NULL);
return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp);
}
@@ -1926,12 +1928,11 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
struct phy_configure_opts_hdmi hdmi = {
.tmds_char_rate = req->rate,
};
- int ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi);
+
+ int ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi, &hdptx->hdmi_cfg);
if (ret)
return ret;
-
- hdptx->hdmi_cfg.rate = req->rate;
}
/*
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (9 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
@ 2026-01-12 23:20 ` Cristian Ciocaltea
2026-01-21 8:52 ` [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Vinod Koul
11 siblings, 0 replies; 16+ messages in thread
From: Cristian Ciocaltea @ 2026-01-12 23:20 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
The PHY is capable of handling four HDMI 2.1 Fixed Rate Link (FRL)
lanes, and each one can operate at any of the rates of 3Gbps, 6Gbps,
8Gbps, 10Gbps or 12Gbps.
Add the necessary driver changes to support the feature.
Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 441 ++++++++++++++++++++--
1 file changed, 418 insertions(+), 23 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index c9942aaf2766..2d973bc37f07 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -22,6 +22,7 @@
#include <linux/reset.h>
#define GRF_HDPTX_CON0 0x00
+#define LC_REF_CLK_SEL BIT(11)
#define HDPTX_I_PLL_EN BIT(7)
#define HDPTX_I_BIAS_EN BIT(6)
#define HDPTX_I_BGR_EN BIT(5)
@@ -322,6 +323,9 @@
#define HDMI14_MAX_RATE 340000000
#define HDMI20_MAX_RATE 600000000
+#define FRL_3G3L_RATE 900000000
+#define FRL_6G3L_RATE 1800000000
+#define FRL_8G4L_RATE 3200000000
enum dp_link_rate {
DP_BW_RBR,
@@ -329,6 +333,22 @@ enum dp_link_rate {
DP_BW_HBR2,
};
+struct lcpll_config {
+ unsigned long long rate;
+ u8 lcvco_mode_en;
+ u8 pi_en;
+ u8 clk_en_100m;
+ u8 pms_mdiv;
+ u8 pms_mdiv_afc;
+ u8 pms_pdiv;
+ u8 pms_refdiv;
+ u8 pms_sdiv;
+ u8 sdm_deno;
+ u8 sdm_num_sign;
+ u8 sdm_num;
+ u8 sdc_n;
+};
+
struct ropll_config {
unsigned long long rate;
u8 pms_mdiv;
@@ -374,6 +394,7 @@ struct rk_hdptx_phy_cfg {
};
struct rk_hdptx_hdmi_cfg {
+ enum phy_hdmi_mode mode;
unsigned long long rate;
unsigned int bpc;
};
@@ -401,6 +422,16 @@ struct rk_hdptx_phy {
unsigned int lanes;
};
+static const struct lcpll_config rk_hdptx_frl_lcpll_cfg[] = {
+ /* | pms | sdm | */
+ /* rate, lcen, pien, cken, mdiv, mdafc, pdiv, rdiv, sdiv, deno, nsig, num, sdcn, */
+ { 4800000000ULL, 1, 0, 0, 125, 125, 1, 1, 0, 1, 0, 0, 2, },
+ { 4000000000ULL, 1, 1, 0, 104, 104, 1, 1, 0, 9, 0, 1, 1, },
+ { 2400000000ULL, 1, 0, 0, 125, 125, 1, 1, 1, 1, 0, 0, 2, },
+ { 1800000000ULL, 1, 0, 0, 125, 125, 1, 1, 1, 1, 0, 0, 2, },
+ { 900000000ULL, 1, 0, 0, 125, 125, 1, 1, 3, 1, 0, 0, 2, },
+};
+
static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
/* | pms | sdm | sdc | */
/* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, num, deno, */
@@ -500,6 +531,110 @@ static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(009a), 0x11),
};
+static const struct reg_sequence rk_hdptx_frl_lcpll_cmn_init_seq[] = {
+ REG_SEQ0(CMN_REG(0011), 0x00),
+ REG_SEQ0(CMN_REG(0017), 0x00),
+ REG_SEQ0(CMN_REG(0025), 0x10),
+ REG_SEQ0(CMN_REG(0026), 0x53),
+ REG_SEQ0(CMN_REG(0027), 0x01),
+ REG_SEQ0(CMN_REG(0028), 0x0d),
+ REG_SEQ0(CMN_REG(002e), 0x02),
+ REG_SEQ0(CMN_REG(002f), 0x0d),
+ REG_SEQ0(CMN_REG(0030), 0x00),
+ REG_SEQ0(CMN_REG(0031), 0x20),
+ REG_SEQ0(CMN_REG(0032), 0x30),
+ REG_SEQ0(CMN_REG(0033), 0x0b),
+ REG_SEQ0(CMN_REG(0034), 0x23),
+ REG_SEQ0(CMN_REG(003d), 0x00),
+ REG_SEQ0(CMN_REG(0042), 0xb8),
+ REG_SEQ0(CMN_REG(0046), 0xff),
+ REG_SEQ0(CMN_REG(0048), 0x44),
+ REG_SEQ0(CMN_REG(004e), 0x14),
+ REG_SEQ0(CMN_REG(0051), 0x00),
+ REG_SEQ0(CMN_REG(0055), 0x00),
+ REG_SEQ0(CMN_REG(0059), 0x11),
+ REG_SEQ0(CMN_REG(005a), 0x03),
+ REG_SEQ0(CMN_REG(005c), 0x05),
+ REG_SEQ0(CMN_REG(005d), 0x0c),
+ REG_SEQ0(CMN_REG(005e), 0x07),
+ REG_SEQ0(CMN_REG(0060), 0x01),
+ REG_SEQ0(CMN_REG(0064), 0x07),
+ REG_SEQ0(CMN_REG(0065), 0x00),
+ REG_SEQ0(CMN_REG(0069), 0x00),
+ REG_SEQ0(CMN_REG(006b), 0x04),
+ REG_SEQ0(CMN_REG(006c), 0x00),
+ REG_SEQ0(CMN_REG(0070), 0x01),
+ REG_SEQ0(CMN_REG(0073), 0x30),
+ REG_SEQ0(CMN_REG(0074), 0x00),
+ REG_SEQ0(CMN_REG(0081), 0x09),
+ REG_SEQ0(CMN_REG(0086), 0x01),
+ REG_SEQ0(CMN_REG(0087), 0x0c),
+ REG_SEQ0(CMN_REG(0089), 0x02),
+ REG_SEQ0(CMN_REG(0095), 0x00),
+ REG_SEQ0(CMN_REG(0097), 0x00),
+ REG_SEQ0(CMN_REG(0099), 0x00),
+ REG_SEQ0(CMN_REG(009b), 0x10),
+};
+
+static const struct reg_sequence rk_hdptx_frl_lcpll_ropll_cmn_init_seq[] = {
+ REG_SEQ0(CMN_REG(0008), 0xd0),
+ REG_SEQ0(CMN_REG(0011), 0x00),
+ REG_SEQ0(CMN_REG(0017), 0x00),
+ REG_SEQ0(CMN_REG(001e), 0x35),
+ REG_SEQ0(CMN_REG(0020), 0x6b),
+ REG_SEQ0(CMN_REG(0021), 0x6b),
+ REG_SEQ0(CMN_REG(0022), 0x11),
+ REG_SEQ0(CMN_REG(0024), 0x00),
+ REG_SEQ0(CMN_REG(0025), 0x10),
+ REG_SEQ0(CMN_REG(0026), 0x53),
+ REG_SEQ0(CMN_REG(0027), 0x15),
+ REG_SEQ0(CMN_REG(0028), 0x0d),
+ REG_SEQ0(CMN_REG(002a), 0x09),
+ REG_SEQ0(CMN_REG(002b), 0x01),
+ REG_SEQ0(CMN_REG(002c), 0x02),
+ REG_SEQ0(CMN_REG(002d), 0x02),
+ REG_SEQ0(CMN_REG(002e), 0x0d),
+ REG_SEQ0(CMN_REG(002f), 0x61),
+ REG_SEQ0(CMN_REG(0030), 0x00),
+ REG_SEQ0(CMN_REG(0031), 0x20),
+ REG_SEQ0(CMN_REG(0032), 0x30),
+ REG_SEQ0(CMN_REG(0033), 0x0b),
+ REG_SEQ0(CMN_REG(0034), 0x23),
+ REG_SEQ0(CMN_REG(0037), 0x00),
+ REG_SEQ0(CMN_REG(003d), 0xc0),
+ REG_SEQ0(CMN_REG(0042), 0xb8),
+ REG_SEQ0(CMN_REG(0046), 0xff),
+ REG_SEQ0(CMN_REG(0048), 0x44),
+ REG_SEQ0(CMN_REG(004e), 0x14),
+ REG_SEQ0(CMN_REG(0054), 0x19),
+ REG_SEQ0(CMN_REG(0058), 0x19),
+ REG_SEQ0(CMN_REG(0059), 0x11),
+ REG_SEQ0(CMN_REG(005b), 0x30),
+ REG_SEQ0(CMN_REG(005c), 0x25),
+ REG_SEQ0(CMN_REG(005d), 0x14),
+ REG_SEQ0(CMN_REG(005e), 0x0e),
+ REG_SEQ0(CMN_REG(0063), 0x01),
+ REG_SEQ0(CMN_REG(0064), 0x0e),
+ REG_SEQ0(CMN_REG(0068), 0x00),
+ REG_SEQ0(CMN_REG(0069), 0x02),
+ REG_SEQ0(CMN_REG(006b), 0x00),
+ REG_SEQ0(CMN_REG(006f), 0x00),
+ REG_SEQ0(CMN_REG(0073), 0x02),
+ REG_SEQ0(CMN_REG(0074), 0x00),
+ REG_SEQ0(CMN_REG(007a), 0x00),
+ REG_SEQ0(CMN_REG(0081), 0x09),
+ REG_SEQ0(CMN_REG(0086), 0x11),
+ REG_SEQ0(CMN_REG(0087), 0x0c),
+ REG_SEQ0(CMN_REG(0089), 0x00),
+ REG_SEQ0(CMN_REG(0095), 0x03),
+ REG_SEQ0(CMN_REG(0097), 0x00),
+ REG_SEQ0(CMN_REG(0099), 0x00),
+ REG_SEQ0(CMN_REG(009b), 0x10),
+ REG_SEQ0(CMN_REG(009e), 0x03),
+ REG_SEQ0(CMN_REG(009f), 0xff),
+ REG_SEQ0(CMN_REG(00a0), 0x60),
+};
+
static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0008), 0x00),
REG_SEQ0(CMN_REG(0011), 0x01),
@@ -553,6 +688,16 @@ static const struct reg_sequence rk_hdptx_common_sb_init_seq[] = {
REG_SEQ0(SB_REG(0117), 0x00),
};
+static const struct reg_sequence rk_hdptx_frl_lntop_init_seq[] = {
+ REG_SEQ0(LNTOP_REG(0200), 0x04),
+ REG_SEQ0(LNTOP_REG(0201), 0x00),
+ REG_SEQ0(LNTOP_REG(0202), 0x00),
+ REG_SEQ0(LNTOP_REG(0203), 0xf0),
+ REG_SEQ0(LNTOP_REG(0204), 0xff),
+ REG_SEQ0(LNTOP_REG(0205), 0xff),
+ REG_SEQ0(LNTOP_REG(0206), 0x05),
+};
+
static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] = {
REG_SEQ0(LNTOP_REG(0201), 0x00),
REG_SEQ0(LNTOP_REG(0202), 0x00),
@@ -624,6 +769,38 @@ static const struct reg_sequence rk_hdptx_common_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0620), 0xa0),
};
+static const struct reg_sequence rk_hdptx_frl_lane_init_seq[] = {
+ REG_SEQ0(LANE_REG(0312), 0x3c),
+ REG_SEQ0(LANE_REG(0412), 0x3c),
+ REG_SEQ0(LANE_REG(0512), 0x3c),
+ REG_SEQ0(LANE_REG(0612), 0x3c),
+ REG_SEQ0(LANE_REG(0303), 0x2f),
+ REG_SEQ0(LANE_REG(0403), 0x2f),
+ REG_SEQ0(LANE_REG(0503), 0x2f),
+ REG_SEQ0(LANE_REG(0603), 0x2f),
+ REG_SEQ0(LANE_REG(0305), 0x03),
+ REG_SEQ0(LANE_REG(0405), 0x03),
+ REG_SEQ0(LANE_REG(0505), 0x03),
+ REG_SEQ0(LANE_REG(0605), 0x03),
+ REG_SEQ0(LANE_REG(0306), 0xfc),
+ REG_SEQ0(LANE_REG(0406), 0xfc),
+ REG_SEQ0(LANE_REG(0506), 0xfc),
+ REG_SEQ0(LANE_REG(0606), 0xfc),
+ REG_SEQ0(LANE_REG(0305), 0x4f),
+ REG_SEQ0(LANE_REG(0405), 0x4f),
+ REG_SEQ0(LANE_REG(0505), 0x4f),
+ REG_SEQ0(LANE_REG(0605), 0x4f),
+ REG_SEQ0(LANE_REG(0304), 0x14),
+ REG_SEQ0(LANE_REG(0404), 0x14),
+ REG_SEQ0(LANE_REG(0504), 0x14),
+ REG_SEQ0(LANE_REG(0604), 0x14),
+ /* Keep Inter-Pair Skew in the limits */
+ REG_SEQ0(LANE_REG(031e), 0x02),
+ REG_SEQ0(LANE_REG(041e), 0x02),
+ REG_SEQ0(LANE_REG(051e), 0x02),
+ REG_SEQ0(LANE_REG(061e), 0x02),
+};
+
static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] = {
REG_SEQ0(LANE_REG(0312), 0x00),
REG_SEQ0(LANE_REG(0412), 0x00),
@@ -787,7 +964,12 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
- regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
+ /* 3 lanes FRL mode */
+ if (hdptx->hdmi_cfg.rate == FRL_6G3L_RATE ||
+ hdptx->hdmi_cfg.rate == FRL_3G3L_RATE)
+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x07);
+ else
+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
(val & HDPTX_O_PHY_RDY) &&
@@ -931,6 +1113,80 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
return true;
}
+static int rk_hdptx_frl_lcpll_cmn_config(struct rk_hdptx_phy *hdptx)
+{
+ const struct lcpll_config *cfg = NULL;
+ int i;
+
+ dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, hdptx->hdmi_cfg.rate);
+
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) {
+ if (hdptx->hdmi_cfg.rate == rk_hdptx_frl_lcpll_cfg[i].rate) {
+ cfg = &rk_hdptx_frl_lcpll_cfg[i];
+ break;
+ }
+ }
+
+ if (!cfg) {
+ dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n",
+ __func__, hdptx->hdmi_cfg.rate);
+ return -EINVAL;
+ }
+
+ rk_hdptx_pre_power_up(hdptx);
+
+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16);
+
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_cmn_init_seq);
+
+ regmap_update_bits(hdptx->regmap, CMN_REG(0008),
+ LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK,
+ FIELD_PREP(LCPLL_EN_MASK, 1) |
+ FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en));
+
+ regmap_update_bits(hdptx->regmap, CMN_REG(001e),
+ LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK,
+ FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) |
+ FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m));
+
+ regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv);
+ regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc);
+ regmap_write(hdptx->regmap, CMN_REG(0022),
+ (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
+ regmap_write(hdptx->regmap, CMN_REG(0023),
+ (cfg->pms_sdiv << 4) | cfg->pms_sdiv);
+ regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno);
+ regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign);
+ regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num);
+
+ regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK,
+ FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n));
+
+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
+ FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
+ regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
+ FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1));
+
+ return rk_hdptx_post_enable_pll(hdptx);
+}
+
+static int rk_hdptx_frl_lcpll_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
+{
+ dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, hdptx->hdmi_cfg.rate);
+
+ rk_hdptx_pre_power_up(hdptx);
+
+ /* ROPLL input reference clock from LCPLL (cascade mode) */
+ regmap_write(hdptx->grf, GRF_HDPTX_CON0,
+ (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL);
+
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_ropll_cmn_init_seq);
+
+ return rk_hdptx_post_enable_pll(hdptx);
+}
+
static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
{
const struct ropll_config *cfg = NULL;
@@ -962,6 +1218,8 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
rk_hdptx_pre_power_up(hdptx);
+ regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16);
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq);
@@ -1000,6 +1258,28 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
return rk_hdptx_post_enable_pll(hdptx);
}
+static int rk_hdptx_pll_cmn_config(struct rk_hdptx_phy *hdptx)
+{
+ if (hdptx->hdmi_cfg.rate <= HDMI20_MAX_RATE)
+ return rk_hdptx_tmds_ropll_cmn_config(hdptx);
+
+ if (hdptx->hdmi_cfg.rate == FRL_8G4L_RATE)
+ return rk_hdptx_frl_lcpll_ropll_cmn_config(hdptx);
+
+ return rk_hdptx_frl_lcpll_cmn_config(hdptx);
+}
+
+static int rk_hdptx_frl_lcpll_mode_config(struct rk_hdptx_phy *hdptx)
+{
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lntop_init_seq);
+
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
+ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lane_init_seq);
+
+ return rk_hdptx_post_enable_lane(hdptx);
+}
+
static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
{
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
@@ -1076,7 +1356,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
if (mode == PHY_MODE_DP) {
rk_hdptx_dp_reset(hdptx);
} else {
- ret = rk_hdptx_tmds_ropll_cmn_config(hdptx);
+ ret = rk_hdptx_pll_cmn_config(hdptx);
if (ret)
goto dec_usage;
}
@@ -1377,7 +1657,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
int ret, lane;
if (mode != PHY_MODE_DP) {
- if (!hdptx->hdmi_cfg.rate) {
+ if (!hdptx->hdmi_cfg.rate && hdptx->hdmi_cfg.mode != PHY_HDMI_MODE_FRL) {
/*
* FIXME: Temporary workaround to setup TMDS char rate
* from the RK DW HDMI QP bridge driver.
@@ -1423,7 +1703,11 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
- ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
+ if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
+ ret = rk_hdptx_frl_lcpll_mode_config(hdptx);
+ else
+ ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
+
if (ret)
rk_hdptx_phy_consumer_put(hdptx, true);
}
@@ -1444,16 +1728,49 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
{
int i;
- if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE)
- return -EINVAL;
+ if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL) {
+ unsigned long long frl_rate = 100000000ULL * hdmi_in->frl.lanes *
+ hdmi_in->frl.rate_per_lane;
- for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
- if (hdmi_in->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
+ switch (hdmi_in->frl.rate_per_lane) {
+ case 3:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
break;
+ default:
+ return -EINVAL;
+ }
- if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
- !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL))
- return -EINVAL;
+ if (!hdmi_in->frl.lanes || hdmi_in->frl.lanes > 4)
+ return -EINVAL;
+
+ if (frl_rate != FRL_8G4L_RATE) {
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++)
+ if (frl_rate == rk_hdptx_frl_lcpll_cfg[i].rate)
+ break;
+ if (i == ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg))
+ return -EINVAL;
+ }
+
+ if (hdmi_out)
+ hdmi_out->rate = frl_rate;
+ } else {
+ if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
+ if (hdmi_in->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
+ break;
+
+ if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
+ !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL))
+ return -EINVAL;
+
+ if (hdmi_out)
+ hdmi_out->rate = hdmi_in->tmds_char_rate;
+ }
switch (hdmi_in->bpc) {
case 0:
@@ -1466,10 +1783,8 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
return -EINVAL;
}
- if (hdmi_out) {
- hdmi_out->rate = hdmi_in->tmds_char_rate;
+ if (hdmi_out)
hdmi_out->bpc = hdmi_in->bpc ?: 8;
- }
return 0;
}
@@ -1729,6 +2044,31 @@ static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx,
return 0;
}
+static int rk_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
+
+ if (mode == PHY_MODE_DP)
+ return 0;
+
+ if (mode != PHY_MODE_HDMI) {
+ dev_err(&phy->dev, "invalid PHY mode: %d\n", mode);
+ return -EINVAL;
+ }
+
+ switch (submode) {
+ case PHY_HDMI_MODE_TMDS:
+ case PHY_HDMI_MODE_FRL:
+ hdptx->hdmi_cfg.mode = submode;
+ break;
+ default:
+ dev_err(&phy->dev, "invalid HDMI mode: %d\n", submode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts)
{
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
@@ -1796,6 +2136,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode,
static const struct phy_ops rk_hdptx_phy_ops = {
.power_on = rk_hdptx_phy_power_on,
.power_off = rk_hdptx_phy_power_off,
+ .set_mode = rk_hdptx_phy_set_mode,
.configure = rk_hdptx_phy_configure,
.validate = rk_hdptx_phy_validate,
.owner = THIS_MODULE,
@@ -1824,17 +2165,62 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx)
{
+ struct lcpll_config lcpll_hw;
struct ropll_config ropll_hw;
u64 fout, sdm;
u32 mode, val;
- int ret;
+ int ret, i;
ret = regmap_read(hdptx->regmap, CMN_REG(0008), &mode);
if (ret)
return 0;
- if (mode & LCPLL_LCVCO_MODE_EN_MASK)
+ if (mode & LCPLL_LCVCO_MODE_EN_MASK) {
+ ret = regmap_read(hdptx->regmap, CMN_REG(0020), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.pms_mdiv = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(0023), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.pms_sdiv = val & 0xf;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(002B), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.sdm_num_sign = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(002C), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.sdm_num = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(002A), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.sdm_deno = val;
+
+ ret = regmap_read(hdptx->regmap, CMN_REG(002D), &val);
+ if (ret)
+ return 0;
+ lcpll_hw.sdc_n = (val & LCPLL_SDC_N_MASK) >> 1;
+
+ for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) {
+ const struct lcpll_config *cfg = &rk_hdptx_frl_lcpll_cfg[i];
+
+ if (cfg->pms_mdiv == lcpll_hw.pms_mdiv &&
+ cfg->pms_sdiv == lcpll_hw.pms_sdiv &&
+ cfg->sdm_num_sign == lcpll_hw.sdm_num_sign &&
+ cfg->sdm_num == lcpll_hw.sdm_num &&
+ cfg->sdm_deno == lcpll_hw.sdm_deno &&
+ cfg->sdc_n == lcpll_hw.sdc_n)
+ return cfg->rate;
+ }
+
+ dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__);
return 0;
+ }
ret = regmap_read(hdptx->regmap, CMN_REG(0051), &val);
if (ret)
@@ -1911,6 +2297,9 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
rate = rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx);
+ if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
+ return rate;
+
return DIV_ROUND_CLOSEST_ULL(rate * 8, hdptx->hdmi_cfg.bpc);
}
@@ -1919,6 +2308,9 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
{
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
+ if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
+ return hdptx->hdmi_cfg.rate;
+
/*
* FIXME: Temporarily allow altering TMDS char rate via CCF.
* To be dropped as soon as the RK DW HDMI QP bridge driver
@@ -1949,23 +2341,26 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
- unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
+ unsigned long long link_rate = rate;
+
+ if (hdptx->hdmi_cfg.mode != PHY_HDMI_MODE_FRL)
+ link_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
- /* Revert any unlikely TMDS char rate change since determine_rate() */
- if (hdptx->hdmi_cfg.rate != tmds_rate) {
+ /* Revert any unlikely link rate change since determine_rate() */
+ if (hdptx->hdmi_cfg.rate != link_rate) {
dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
- tmds_rate, hdptx->hdmi_cfg.rate);
- hdptx->hdmi_cfg.rate = tmds_rate;
+ link_rate, hdptx->hdmi_cfg.rate);
+ hdptx->hdmi_cfg.rate = link_rate;
}
/*
- * The TMDS char rate would be normally programmed in HW during
+ * The link rate would be normally programmed in HW during
* phy_ops.power_on() or clk_ops.prepare() callbacks, but it might
* happen that the former gets fired too late, i.e. after this call,
* while the latter being executed only once, i.e. when clock remains
* in the prepared state during rate changes.
*/
- return rk_hdptx_tmds_ropll_cmn_config(hdptx);
+ return rk_hdptx_pll_cmn_config(hdptx);
}
static const struct clk_ops hdptx_phy_clk_ops = {
--
2.52.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment
2026-01-12 23:20 ` [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
@ 2026-01-13 8:11 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2026-01-13 8:11 UTC (permalink / raw)
To: Cristian Ciocaltea, Vinod Koul, Kishon Vijay Abraham I,
Heiko Stuebner, Algea Cao, Dmitry Baryshkov
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
On 1/13/26 00:20, Cristian Ciocaltea wrote:
> Handle a bunch of reported checkpatch.pl complaints:
>
> CHECK: Alignment should match open parenthesis
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 89710066d70c..3f8a7f4f5cd8 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
> LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
> LN_TX_JEQ_ODD_CTRL_RBR_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_RBR_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
> @@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
> LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
> LN_TX_JEQ_ODD_CTRL_HBR_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_HBR_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
> @@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
> LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
> LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_HBR2_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
2026-01-12 23:20 ` [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
@ 2026-01-13 8:12 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2026-01-13 8:12 UTC (permalink / raw)
To: Cristian Ciocaltea, Vinod Koul, Kishon Vijay Abraham I,
Heiko Stuebner, Algea Cao, Dmitry Baryshkov
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
On 1/13/26 00:20, Cristian Ciocaltea wrote:
> Fix the naming inconsistencies for some of the functions and global
> variables:
>
> * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable
> * Replace '_ropll_tmds_' with '_tmds_ropll_' globally
> * Replace 'hdtpx' with 'hdptx' globally
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 62 +++++++++++------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 3f8a7f4f5cd8..3c6eb6dbadd0 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -32,17 +32,17 @@
> #define HDPTX_O_PHY_RDY BIT(1)
> #define HDPTX_O_SB_RDY BIT(0)
>
> -#define HDTPX_REG(_n, _min, _max) \
> +#define HDPTX_REG(_n, _min, _max) \
> ( \
> BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
> BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
> ((0x##_n) * 4) \
> )
>
> -#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
> -#define SB_REG(n) HDTPX_REG(n, 0100, 0129)
> -#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
> -#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
> +#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7)
> +#define SB_REG(n) HDPTX_REG(n, 0100, 0129)
> +#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229)
> +#define LANE_REG(n) HDPTX_REG(n, 0300, 062d)
>
> /* CMN_REG(0008) */
> #define OVRD_LCPLL_EN_MASK BIT(7)
> @@ -397,7 +397,7 @@ struct rk_hdptx_phy {
> unsigned int lanes;
> };
>
> -static const struct ropll_config ropll_tmds_cfg[] = {
> +static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
> /* | pms | sdm | sdc | */
> /* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, num, deno, */
> { 594000000ULL, 124, 124, 1, 1, 0, 1, 62, 1, 16, 5, 0, 1, },
> @@ -424,7 +424,7 @@ static const struct ropll_config ropll_tmds_cfg[] = {
> { 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, 1, 1, },
> };
>
> -static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
> +static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
> REG_SEQ0(CMN_REG(0009), 0x0c),
> REG_SEQ0(CMN_REG(000a), 0x83),
> REG_SEQ0(CMN_REG(000b), 0x06),
> @@ -514,7 +514,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
> REG_SEQ0(CMN_REG(009b), 0x10),
> };
>
> -static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
> +static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
> REG_SEQ0(CMN_REG(0008), 0x00),
> REG_SEQ0(CMN_REG(0011), 0x01),
> REG_SEQ0(CMN_REG(0017), 0x20),
> @@ -556,14 +556,14 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
> REG_SEQ0(CMN_REG(009b), 0x00),
> };
>
> -static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
> +static const struct reg_sequence rk_hdptx_common_sb_init_seq[] = {
> REG_SEQ0(SB_REG(0114), 0x00),
> REG_SEQ0(SB_REG(0115), 0x00),
> REG_SEQ0(SB_REG(0116), 0x00),
> REG_SEQ0(SB_REG(0117), 0x00),
> };
>
> -static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
> +static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] = {
> REG_SEQ0(LNTOP_REG(0201), 0x00),
> REG_SEQ0(LNTOP_REG(0202), 0x00),
> REG_SEQ0(LNTOP_REG(0203), 0x0f),
> @@ -571,7 +571,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
> REG_SEQ0(LNTOP_REG(0205), 0xff),
> };
>
> -static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
> +static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] = {
> REG_SEQ0(LNTOP_REG(0201), 0x07),
> REG_SEQ0(LNTOP_REG(0202), 0xc1),
> REG_SEQ0(LNTOP_REG(0203), 0xf0),
> @@ -579,7 +579,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
> REG_SEQ0(LNTOP_REG(0205), 0x1f),
> };
>
> -static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
> +static const struct reg_sequence rk_hdptx_common_lane_init_seq[] = {
> REG_SEQ0(LANE_REG(0303), 0x0c),
> REG_SEQ0(LANE_REG(0307), 0x20),
> REG_SEQ0(LANE_REG(030a), 0x17),
> @@ -634,7 +634,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
> REG_SEQ0(LANE_REG(0620), 0xa0),
> };
>
> -static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
> +static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] = {
> REG_SEQ0(LANE_REG(0312), 0x00),
> REG_SEQ0(LANE_REG(0412), 0x00),
> REG_SEQ0(LANE_REG(0512), 0x00),
> @@ -938,7 +938,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
> return true;
> }
>
> -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
> +static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
> {
> const struct ropll_config *cfg = NULL;
> struct ropll_config rc = {0};
> @@ -947,9 +947,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
> if (!hdptx->hdmi_cfg.tmds_char_rate)
> return 0;
>
> - for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
> - if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
> - cfg = &ropll_tmds_cfg[i];
> + for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
> + if (hdptx->hdmi_cfg.tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
> + cfg = &rk_hdptx_tmds_ropll_cfg[i];
> break;
> }
>
> @@ -969,8 +969,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
>
> rk_hdptx_pre_power_up(hdptx);
>
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq);
>
> regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
> regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
> @@ -1012,25 +1012,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
> return ret;
> }
>
> -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
> +static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
> {
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
>
> regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
>
> if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
> /* For 1/40 bitrate clk */
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq);
> } else {
> /* For 1/10 bitrate clk */
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq);
> }
>
> regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
> regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
>
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
> - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
> + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
>
> return rk_hdptx_post_enable_lane(hdptx);
> }
> @@ -1089,7 +1089,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
> if (mode == PHY_MODE_DP) {
> rk_hdptx_dp_reset(hdptx);
> } else {
> - ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
> + ret = rk_hdptx_tmds_ropll_cmn_config(hdptx);
> if (ret)
> goto dec_usage;
> }
> @@ -1436,7 +1436,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
> regmap_write(hdptx->grf, GRF_HDPTX_CON0,
> HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
>
> - ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
> + ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
> if (ret)
> rk_hdptx_phy_consumer_put(hdptx, true);
> }
> @@ -1459,11 +1459,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
> if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
> return -EINVAL;
>
> - for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
> - if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate)
> + for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
> + if (hdmi->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
> break;
>
> - if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
> + if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
> !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
> return -EINVAL;
>
> @@ -1891,7 +1891,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> * while the latter being executed only once, i.e. when clock remains
> * in the prepared state during rate changes.
> */
> - return rk_hdptx_ropll_tmds_cmn_config(hdptx);
> + return rk_hdptx_tmds_ropll_cmn_config(hdptx);
> }
>
> static const struct clk_ops hdptx_phy_clk_ops = {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()
2026-01-12 23:20 ` [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
@ 2026-01-13 8:13 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2026-01-13 8:13 UTC (permalink / raw)
To: Cristian Ciocaltea, Vinod Koul, Kishon Vijay Abraham I,
Heiko Stuebner, Algea Cao, Dmitry Baryshkov
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
On 1/13/26 00:20, Cristian Ciocaltea wrote:
> rk_hdptx_dp_reset() is allowed to sleep, hence replace the busy waiting
> with usleep_range(), to allow other threads to run.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index a65e96694237..89710066d70c 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -1042,7 +1042,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
> reset_control_assert(hdptx->rsts[RST_INIT].rstc);
>
> reset_control_assert(hdptx->rsts[RST_APB].rstc);
> - udelay(10);
> + usleep_range(10, 15);
> reset_control_deassert(hdptx->rsts[RST_APB].rstc);
>
> regmap_update_bits(hdptx->regmap, LANE_REG(0301),
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
` (10 preceding siblings ...)
2026-01-12 23:20 ` [PATCH v6 11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
@ 2026-01-21 8:52 ` Vinod Koul
11 siblings, 0 replies; 16+ messages in thread
From: Vinod Koul @ 2026-01-21 8:52 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Heiko Stuebner, Algea Cao,
Dmitry Baryshkov, Neil Armstrong, Cristian Ciocaltea
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
On Tue, 13 Jan 2026 01:20:47 +0200, Cristian Ciocaltea wrote:
> The Samsung HDMI/eDP Transmitter Combo PHY is capable of handling four
> HDMI 2.1 Fixed Rate Link (FRL) lanes, while each lane can operate at
> 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps.
>
> This patchset extends the HDMI PHY configuration API to manage the FRL
> mode and provides all the required HDMI driver changes to enable FRL in
> addition to the already supported TMDS mode.
>
> [...]
Applied, thanks!
[01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options
commit: 41c6cac6decd5123db1da8ca240a9c808b0ae6ce
[02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()
commit: 0ef8dd1034e3656e40d020911bb7aa14e7084663
[03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment
commit: 4f310f180373bd0e68311debee7a0dddb14c1656
[04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
commit: 925f26a4f8c65e5686e1820f0bdc7e0a237edba7
[05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper
commit: 8e8aa072b19d0d16afbfd690c8e50628176db3ef
[06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
commit: df74a964e4354e65fefef60c9c50765ff32cd26e
[07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
commit: 3481fc04d969bc1528c2d1f7c02443a9fccf1a83
[08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data
commit: 66d76b6d958d7ca195c8b3f43828b12a206fb731
[09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
commit: ac079c1207e492924237fdfb12c93664265b2e23
[10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
commit: b14fec4dbda301d61603c047277b4f447837b3e3
[11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
commit: de5dba83311842cf208735b37bea84073688d470
Best regards,
--
~Vinod
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-01-21 8:52 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
2026-01-13 8:13 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
2026-01-13 8:11 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
2026-01-13 8:12 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
2026-01-21 8:52 ` [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Vinod Koul
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