From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Jun Nie <jun.nie@linaro.org>, Rob Clark <robdclark@gmail.com>,
"Abhinav Kumar" <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 04/15] drm/msm/dpu: polish log for resource allocation
Date: Fri, 14 Feb 2025 16:25:08 -0800 [thread overview]
Message-ID: <ebea664b-6f53-440a-aa2f-4d4991fb5e1f@quicinc.com> (raw)
In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-4-9701a16340da@linaro.org>
On 1/17/2025 8:00 AM, Jun Nie wrote:
> It is more likely that resource allocation may fail in complex usage
> case, such as quad-pipe case, than existing usage cases.
> A resource type ID is printed on failure in the current implementation,
> but the raw ID number is not explicit enough to help easily understand
> which resource caused the failure, so add a table to match the type ID
> to an human readable resource name and use it in the error print.
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index a67ad58acd99f..24e085437039e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -802,6 +802,21 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *global_state,
> ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id);
> }
>
> +static char *dpu_hw_blk_type_name[] = {
> + [DPU_HW_BLK_TOP] = "TOP",
> + [DPU_HW_BLK_SSPP] = "SSPP",
> + [DPU_HW_BLK_LM] = "LM",
> + [DPU_HW_BLK_CTL] = "CTL",
> + [DPU_HW_BLK_PINGPONG] = "pingpong",
> + [DPU_HW_BLK_INTF] = "INTF",
> + [DPU_HW_BLK_WB] = "WB",
> + [DPU_HW_BLK_DSPP] = "DSPP",
> + [DPU_HW_BLK_MERGE_3D] = "merge_3d",
> + [DPU_HW_BLK_DSC] = "DSC",
> + [DPU_HW_BLK_CDM] = "CDM",
> + [DPU_HW_BLK_MAX] = "unknown",
> +};
> +
> /**
> * dpu_rm_get_assigned_resources - Get hw resources of the given type that are
> * assigned to this encoder
> @@ -862,13 +877,13 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
> continue;
>
> if (num_blks == blks_size) {
> - DPU_ERROR("More than %d resources assigned to enc %d\n",
> - blks_size, enc_id);
> + DPU_ERROR("More than %d %s assigned to enc %d\n",
> + blks_size, dpu_hw_blk_type_name[type], enc_id);
> break;
> }
> if (!hw_blks[i]) {
> - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n",
> - type, enc_id);
> + DPU_ERROR("%s unavailable to assign to enc %d\n",
> + dpu_hw_blk_type_name[type], enc_id);
> break;
> }
> blks[num_blks++] = hw_blks[i];
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-02-15 0:25 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-17 16:00 [PATCH v5 00/15] drm/msm/dpu: Support quad pipe with dual-DSI Jun Nie
2025-01-17 16:00 ` [PATCH v5 01/15] drm/msm/dpu: check every pipe per capability Jun Nie
2025-01-17 16:00 ` [PATCH v5 02/15] drm/msm/dpu: Do not fix number of DSC Jun Nie
2025-02-07 1:12 ` Jessica Zhang
2025-01-17 16:00 ` [PATCH v5 03/15] drm/msm/dpu: configure DSC per number in use Jun Nie
2025-02-07 1:14 ` Jessica Zhang
2025-01-17 16:00 ` [PATCH v5 04/15] drm/msm/dpu: polish log for resource allocation Jun Nie
2025-02-15 0:25 ` Jessica Zhang [this message]
2025-01-17 16:00 ` [PATCH v5 05/15] drm/msm/dpu: decide right side per last bit Jun Nie
2025-02-15 0:29 ` Jessica Zhang
2025-01-17 16:00 ` [PATCH v5 06/15] drm/msm/dpu: fix mixer number counter on allocation Jun Nie
2025-02-15 0:48 ` Jessica Zhang
2025-01-17 16:00 ` [PATCH v5 07/15] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Jun Nie
2025-01-17 16:00 ` [PATCH v5 08/15] drm/msm/dpu: bind correct pingpong for quad pipe Jun Nie
2025-01-20 13:15 ` Marijn Suijten
2025-01-20 23:24 ` Jun Nie
2025-01-17 16:00 ` [PATCH v5 09/15] drm/msm/dpu: Add pipe as trace argument Jun Nie
2025-02-15 0:33 ` Jessica Zhang
2025-01-17 16:00 ` [PATCH v5 10/15] drm/msm/dpu: handle pipes as array Jun Nie
2025-01-17 16:00 ` [PATCH v5 11/15] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Jun Nie
2025-01-17 16:00 ` [PATCH v5 12/15] drm/msm/dpu: blend pipes per mixer pairs config Jun Nie
2025-01-17 16:00 ` [PATCH v5 13/15] drm/msm/dpu: support SSPP assignment for quad-pipe case Jun Nie
2025-01-17 16:00 ` [PATCH v5 14/15] drm/msm/dpu: support plane splitting in " Jun Nie
2025-01-17 16:00 ` [PATCH v5 15/15] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Jun Nie
2025-01-23 23:31 ` [PATCH v5 00/15] drm/msm/dpu: Support quad pipe with dual-DSI Jessica Zhang
2025-01-24 18:07 ` Jun Nie
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