From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: neil.armstrong@linaro.org, Konrad Dybcio <konradybcio@kernel.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <lumag@kernel.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: Re: [PATCH RFT v6 1/5] drm/msm/adreno: Implement SMEM-based speed bin
Date: Wed, 30 Apr 2025 18:25:23 +0200 [thread overview]
Message-ID: <ee44260b-13cb-4901-a073-2b9bfac2a794@oss.qualcomm.com> (raw)
In-Reply-To: <68a2cb9d-4f3b-4bfa-81c3-2d5c95a837f3@linaro.org>
On 4/30/25 6:20 PM, neil.armstrong@linaro.org wrote:
> On 30/04/2025 13:34, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@linaro.org>
>>
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add support for SMEM-based speed binning, which includes getting
>> "feature code" and "product code" from said source and parsing them
>> to form something that lets us match OPPs against.
>>
>> Due to the product code being ignored in the context of Adreno on
>> production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */
>
> This should be SM8550
No, this is 8650 to signify that this holds true even later
Looking into it, I can even say 8750 here now
Konrad
next prev parent reply other threads:[~2025-04-30 16:25 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-30 11:34 [RFT PATCH v6 0/5] Add SMEM-based speedbin matching Konrad Dybcio
2025-04-30 11:34 ` [PATCH RFT v6 1/5] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2025-04-30 16:20 ` neil.armstrong
2025-04-30 16:25 ` Konrad Dybcio [this message]
2025-04-30 11:34 ` [PATCH RFT v6 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Konrad Dybcio
2025-04-30 12:26 ` neil.armstrong
2025-04-30 12:35 ` Konrad Dybcio
2025-04-30 12:49 ` neil.armstrong
2025-04-30 13:09 ` Konrad Dybcio
2025-04-30 14:49 ` neil.armstrong
2025-04-30 15:36 ` Konrad Dybcio
2025-04-30 16:19 ` neil.armstrong
2025-04-30 16:39 ` Konrad Dybcio
2025-04-30 16:56 ` neil.armstrong
2025-05-01 9:29 ` Akhil P Oommen
2025-05-01 15:53 ` Konrad Dybcio
2025-05-11 9:51 ` Akhil P Oommen
2025-05-22 16:02 ` Konrad Dybcio
2025-05-22 17:33 ` Rob Clark
2025-04-30 11:34 ` [PATCH RFT v6 3/5] drm/msm/adreno: Define A530 speed bins explicitly Konrad Dybcio
2025-04-30 11:34 ` [PATCH RFT v6 4/5] drm/msm/adreno: Redo the speedbin assignment Konrad Dybcio
2025-04-30 11:34 ` [PATCH RFT v6 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Konrad Dybcio
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