mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
	<dave.jiang@intel.com>, <alison.schofield@intel.com>,
	<dan.j.williams@intel.com>, <bhelgaas@google.com>,
	<shiju.jose@huawei.com>, <ming.li@zohomail.com>,
	<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,
	<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,
	<lukas@wunner.de>, <sathyanarayanan.kuppuswamy@linux.intel.com>,
	<linux-cxl@vger.kernel.org>, <alucerop@amd.com>,
	<ira.weiny@intel.com>
Subject: Re: [PATCH v12 25/25] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup
Date: Fri, 3 Oct 2025 15:12:05 -0500	[thread overview]
Message-ID: <f70d062f-0889-4ae4-93f7-f2c7578b8bf3@amd.com> (raw)
In-Reply-To: <20250925223440.3539069-26-terry.bowman@amd.com>

On 9/25/2025 5:34 PM, Terry Bowman wrote:
> During CXL device cleanup the CXL PCIe Port device interrupts remain
> enabled. This potentially allows unnecessary interrupt processing on
> behalf of the CXL errors while the device is destroyed.
> 
> Disable CXL protocol errors by setting the CXL devices' AER mask register.
> 
> Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal_errors().
> Add to the AER service driver allowing other subsystems to use.
> 
> Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors().
> Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL
> Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL
> Endpoints. Follow the same "bottom-up" approach used during CXL Port
> teardown.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> 
> ---
> 
> Changes in v11->v12:
> - Keep pci_aer_mask_internal_errors() in driver/pci/pcie/aer.c (Lukas)
> - Update commit description for pci_aer_mask_internal_errors()
> - Add check `if (port->parent_dport)` in delete_switch_port() (Terry)
> 
> Changes in v10->v11:
> - Removed guard() cxl_mask_proto_interrupts(). RP was blocking during
>   testing. (Terry)
> ---
>  drivers/cxl/core/core.h |  2 ++
>  drivers/cxl/core/port.c | 10 +++++++++-
>  drivers/cxl/core/ras.c  |  7 +++++++
>  drivers/pci/pcie/aer.c  | 21 +++++++++++++++++++++
>  include/linux/aer.h     |  2 ++
>  5 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 3197a71bf7b8..db318a81034a 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -158,6 +158,7 @@ void cxl_cor_error_detected(struct device *dev);
>  pci_ers_result_t cxl_error_detected(struct device *dev);
>  void cxl_port_cor_error_detected(struct device *dev);
>  pci_ers_result_t cxl_port_error_detected(struct device *dev);
> +void cxl_mask_proto_interrupts(struct device *dev);
>  #else
>  static inline int cxl_ras_init(void)
>  {
> @@ -187,6 +188,7 @@ static inline pci_ers_result_t cxl_port_error_detected(struct device *dev)
>  {
>  	return PCI_ERS_RESULT_NONE;
>  }
> +static inline void cxl_mask_proto_interrupts(struct device *dev) { }
>  #endif // CONFIG_CXL_RAS
>  
>  int cxl_gpf_port_setup(struct cxl_dport *dport);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index f34a44abb2c9..337a165e8dcd 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1434,6 +1434,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL");
>   */
>  static void delete_switch_port(struct cxl_port *port)
>  {
> +	cxl_mask_proto_interrupts(port->uport_dev);
> +	if (port->parent_dport)
> +		cxl_mask_proto_interrupts(port->parent_dport->dport_dev);
> +
>  	devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port);
>  	devm_release_action(port->dev.parent, cxl_unlink_uport, port);
>  	devm_release_action(port->dev.parent, unregister_port, port);
> @@ -1455,8 +1459,10 @@ static void del_dports(struct cxl_port *port)
>  
>  	device_lock_assert(&port->dev);
>  
> -	xa_for_each(&port->dports, index, dport)
> +	xa_for_each(&port->dports, index, dport) {
> +		cxl_mask_proto_interrupts(dport->dport_dev);

Should this call get moved into del_dport()? I think the dports can get
deleted as the downstream devices leave, which would skip masking the protocol interrupts
on said dports.

If that's not the case, then:
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>

>  		del_dport(dport);
> +	}


      reply	other threads:[~2025-10-03 20:12 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-25 22:34 [PATCH v12 00/25] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-09-25 22:34 ` [PATCH v12 01/25] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-09-25 22:34 ` [PATCH v12 02/25] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-10-01 15:09   ` Jonathan Cameron
2025-09-25 22:34 ` [PATCH v12 03/25] cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c Terry Bowman
2025-10-03 20:11   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 04/25] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS Terry Bowman
2025-09-25 23:17   ` Dave Jiang
2025-10-01 15:11   ` Jonathan Cameron
2025-09-25 22:34 ` [PATCH v12 05/25] cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block Terry Bowman
2025-09-25 23:31   ` Dave Jiang
2025-10-01 15:23     ` Jonathan Cameron
2025-09-25 22:34 ` [PATCH v12 06/25] CXL/AER: Introduce aer_cxl_rch.c into AER driver for handling CXL RCH errors Terry Bowman
2025-09-25 23:36   ` Dave Jiang
2025-09-26 12:32   ` kernel test robot
2025-10-01 15:42   ` Jonathan Cameron
2025-09-25 22:34 ` [PATCH v12 07/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-09-25 23:53   ` Dave Jiang
2025-10-01 15:58   ` Jonathan Cameron
2025-10-02 15:25     ` Bowman, Terry
2025-10-03 20:11       ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 08/25] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-09-25 22:34 ` [PATCH v12 09/25] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-10-03 20:11   ` Cheatham, Benjamin
2025-10-06 19:59     ` Bowman, Terry
2025-09-25 22:34 ` [PATCH v12 10/25] CXL/AER: Update PCI class code check to use FIELD_GET() Terry Bowman
2025-09-26  0:02   ` Dave Jiang
2025-10-01 16:12   ` Jonathan Cameron
2025-10-02  7:40     ` Lukas Wunner
2025-10-30 17:16       ` Bowman, Terry
2025-10-31  5:30         ` Lukas Wunner
2025-09-25 22:34 ` [PATCH v12 11/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-10-03 20:11   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 12/25] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-10-03 20:11   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 13/25] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-09-26 20:44   ` Dave Jiang
2025-09-25 22:34 ` [PATCH v12 14/25] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-10-03 20:11   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 15/25] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-09-26 21:10   ` Dave Jiang
2025-10-24 10:25     ` Alejandro Lucero Palau
2025-10-24 17:15       ` Dave Jiang
2025-10-24 19:40       ` Bowman, Terry
2025-10-27 16:33         ` Alejandro Lucero Palau
2025-09-25 22:34 ` [PATCH v12 16/25] CXL/PCI: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2025-09-26 21:26   ` Dave Jiang
2025-10-01 16:14   ` Jonathan Cameron
2025-10-03 20:11   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 17/25] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-09-26 22:04   ` Dave Jiang
2025-09-30 14:06     ` Bowman, Terry
2025-09-30 16:09       ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-10-06 21:07     ` Bowman, Terry
2025-09-25 22:34 ` [PATCH v12 18/25] CXL/AER: Introduce aer_cxl_vh.c in AER driver for forwarding CXL errors Terry Bowman
2025-09-26 22:56   ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 19/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Terry Bowman
2025-09-26 23:02   ` Dave Jiang
2025-10-02 12:27   ` Jonathan Cameron
2025-10-03 20:12   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 20/25] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-09-26 23:26   ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-10-06 20:17     ` Dave Jiang
2025-09-25 22:34 ` [PATCH v12 21/25] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-09-29 23:32   ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-10-06 21:28     ` Bowman, Terry
2025-09-25 22:34 ` [PATCH v12 22/25] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-09-26 15:01   ` kernel test robot
2025-09-26 18:10   ` kernel test robot
2025-09-25 22:34 ` [PATCH v12 23/25] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-09-30  0:26   ` Dave Jiang
2025-09-30 14:38     ` Bowman, Terry
2025-09-30 16:13       ` Dave Jiang
2025-09-30 16:43         ` Bowman, Terry
2025-09-30 16:46           ` Dave Jiang
2025-10-01 13:58             ` Bowman, Terry
2025-10-01 15:33               ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 24/25] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-09-30  0:28   ` Dave Jiang
2025-10-03 20:12   ` Cheatham, Benjamin
2025-09-25 22:34 ` [PATCH v12 25/25] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-10-03 20:12   ` Cheatham, Benjamin [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f70d062f-0889-4ae4-93f7-f2c7578b8bf3@amd.com \
    --to=benjamin.cheatham@amd.com \
    --cc=PradeepVineshReddy.Kodamati@amd.com \
    --cc=Smita.KoralahalliChannabasappa@amd.com \
    --cc=alison.schofield@intel.com \
    --cc=alucerop@amd.com \
    --cc=bhelgaas@google.com \
    --cc=dan.carpenter@linaro.org \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=ira.weiny@intel.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lukas@wunner.de \
    --cc=ming.li@zohomail.com \
    --cc=rrichter@amd.com \
    --cc=sathyanarayanan.kuppuswamy@linux.intel.com \
    --cc=shiju.jose@huawei.com \
    --cc=terry.bowman@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®