From: "Huang, Kai" <kai.huang@intel.com>
To: "Gao, Chao" <chao.gao@intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"ashish.kalra@amd.com" <ashish.kalra@amd.com>,
"Hansen, Dave" <dave.hansen@intel.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"mingo@redhat.com" <mingo@redhat.com>,
"dwmw@amazon.co.uk" <dwmw@amazon.co.uk>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"seanjc@google.com" <seanjc@google.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"kas@kernel.org" <kas@kernel.org>,
"Chatre, Reinette" <reinette.chatre@intel.com>,
"Yamahata, Isaku" <isaku.yamahata@intel.com>,
"nik.borisov@suse.com" <nik.borisov@suse.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"peterz@infradead.org" <peterz@infradead.org>,
"sagis@google.com" <sagis@google.com>,
"Chen, Farrah" <farrah.chen@intel.com>,
"Edgecombe, Rick P" <rick.p.edgecombe@intel.com>,
"bp@alien8.de" <bp@alien8.de>, "x86@kernel.org" <x86@kernel.org>,
"Williams, Dan J" <dan.j.williams@intel.com>
Subject: Re: [PATCH v5 3/7] x86/virt/tdx: Mark memory cache state incoherent when making SEAMCALL
Date: Mon, 4 Aug 2025 12:47:56 +0000 [thread overview]
Message-ID: <f9631567afe3e72e7a99724092426cc06e887ed6.camel@intel.com> (raw)
In-Reply-To: <aIx5jcdZ32mjOfXg@intel.com>
On Fri, 2025-08-01 at 16:23 +0800, Chao Gao wrote:
> On Tue, Jul 29, 2025 at 12:28:37AM +1200, Kai Huang wrote:
> > On TDX platforms, dirty cacheline aliases with and without encryption
> > bits can coexist, and the cpu can flush them back to memory in random
> > order. During kexec, the caches must be flushed before jumping to the
> > new kernel otherwise the dirty cachelines could silently corrupt the
> > memory used by the new kernel due to different encryption property.
> >
> > A percpu boolean is used to mark whether the cache of a given CPU may be
> > in an incoherent state, and the kexec performs WBINVD on the CPUs with
> > that boolean turned on.
> >
> > For TDX, only the TDX module or the TDX guests can generate dirty
> > cachelines of TDX private memory, i.e., they are only generated when the
> > kernel does a SEAMCALL.
> >
> > Set that boolean when the kernel does SEAMCALL so that kexec can flush
> > the cache correctly.
> >
> > The kernel provides both the __seamcall*() assembly functions and the
> > seamcall*() wrapper ones which additionally handle running out of
> > entropy error in a loop. Most of the SEAMCALLs are called using the
> > seamcall*(), except TDH.VP.ENTER and TDH.PHYMEM.PAGE.RDMD which are
> > called using __seamcall*() variant directly.
> >
> > To cover the two special cases, add a new helper do_seamcall() which
> > only sets the percpu boolean and then calls the __seamcall*(), and
> > change the special cases to use do_seamcall(). To cover all other
> > SEAMCALLs, change seamcall*() to call do_seamcall().
> >
> > For the SEAMCALLs invoked via seamcall*(), they can be made from both
> > task context and IRQ disabled context. Given SEAMCALL is just a lengthy
> > instruction (e.g., thousands of cycles) from kernel's point of view and
> > preempt_{disable|enable}() is cheap compared to it, just unconditionally
> > disable preemption during setting the boolean and making SEAMCALL.
> >
> > Signed-off-by: Kai Huang <kai.huang@intel.com>
> > Tested-by: Farrah Chen <farrah.chen@intel.com>
>
> Reviewed-by: Chao Gao <chao.gao@intel.com>
>
> One small question below,
>
> <snip>
>
> > +static __always_inline u64 do_seamcall(sc_func_t func, u64 fn,
> > + struct tdx_module_args *args)
> > +{
> > + lockdep_assert_preemption_disabled();
> > +
> > + /*
> > + * SEAMCALLs are made to the TDX module and can generate dirty
> > + * cachelines of TDX private memory. Mark cache state incoherent
> > + * so that the cache can be flushed during kexec.
> > + *
> > + * This needs to be done before actually making the SEAMCALL,
>
> ...
>
> > + * because kexec-ing CPU could send NMI to stop remote CPUs,
> > + * in which case even disabling IRQ won't help here.
> > + */
> > + this_cpu_write(cache_state_incoherent, true);
>
> I'm not sure this write is guaranteed to occur before the SEAMCALL, as I don't
> see any explicit barrier to prevent the compiler from reordering them. Do you
> think this is an issue?
AFAICT this_cpu_write() eventually ended up with "volatile" being used, so
it has a compiler barrier already.
Plus what right after this_cpu_write() is a function call, with the body
actually implemented in another file, so I don't think the compiler is
smart enough to do any reordering here.
>
> > +
> > + return func(fn, args);
> > +}
> > +
next prev parent reply other threads:[~2025-08-04 12:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-28 12:28 [PATCH v5 0/7] TDX host: kexec/kdump support Kai Huang
2025-07-28 12:28 ` [PATCH v5 1/7] x86/kexec: Consolidate relocate_kernel() function parameters Kai Huang
2025-08-06 6:53 ` Huang, Kai
2025-08-06 13:00 ` Tom Lendacky
2025-08-06 22:29 ` Huang, Kai
2025-07-28 12:28 ` [PATCH v5 2/7] x86/sme: Use percpu boolean to control WBINVD during kexec Kai Huang
2025-07-28 12:28 ` [PATCH v5 3/7] x86/virt/tdx: Mark memory cache state incoherent when making SEAMCALL Kai Huang
2025-08-01 8:23 ` Chao Gao
2025-08-04 12:47 ` Huang, Kai [this message]
2025-08-12 0:51 ` Edgecombe, Rick P
2025-08-12 1:32 ` Huang, Kai
2025-08-12 1:34 ` Edgecombe, Rick P
2025-08-12 2:03 ` Huang, Kai
2025-08-14 0:09 ` Huang, Kai
2025-07-28 12:28 ` [PATCH v5 4/7] x86/kexec: Disable kexec/kdump on platforms with TDX partial write erratum Kai Huang
2025-07-28 12:28 ` [PATCH v5 5/7] x86/virt/tdx: Remove the !KEXEC_CORE dependency Kai Huang
2025-07-28 12:28 ` [PATCH v5 6/7] x86/virt/tdx: Update the kexec section in the TDX documentation Kai Huang
2025-07-28 12:28 ` [PATCH v5 7/7] KVM: TDX: Explicitly do WBINVD when no more TDX SEAMCALLs Kai Huang
2025-08-01 8:30 ` Chao Gao
2025-08-04 12:48 ` Huang, Kai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f9631567afe3e72e7a99724092426cc06e887ed6.camel@intel.com \
--to=kai.huang@intel.com \
--cc=ashish.kalra@amd.com \
--cc=bp@alien8.de \
--cc=chao.gao@intel.com \
--cc=dan.j.williams@intel.com \
--cc=dave.hansen@intel.com \
--cc=dwmw@amazon.co.uk \
--cc=farrah.chen@intel.com \
--cc=hpa@zytor.com \
--cc=isaku.yamahata@intel.com \
--cc=kas@kernel.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=nik.borisov@suse.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=reinette.chatre@intel.com \
--cc=rick.p.edgecombe@intel.com \
--cc=sagis@google.com \
--cc=seanjc@google.com \
--cc=tglx@linutronix.de \
--cc=thomas.lendacky@amd.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®