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From: "tip-bot for mike.travis@hpe.com" <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tglx@linutronix.de, bin.gao@linux.intel.com,
	dimitri.sivanich@hpe.com, andrew.banman@hpe.com,
	mingo@kernel.org, mike.travis@hpe.com, prarit@redhat.com,
	peterz@infradead.org, hpa@zytor.com, russ.anderson@hpe.com,
	linux-kernel@vger.kernel.org
Subject: [tip:x86/timers] x86/tsc: Drastically reduce the number of firmware bug warnings
Date: Mon, 16 Oct 2017 14:16:46 -0700	[thread overview]
Message-ID: <tip-41e7864ab5ce4ec36e89a9f55d8d9dfe19b0392c@git.kernel.org> (raw)
In-Reply-To: <20171012163202.175062400@stormcage.americas.sgi.com>

Commit-ID:  41e7864ab5ce4ec36e89a9f55d8d9dfe19b0392c
Gitweb:     https://git.kernel.org/tip/41e7864ab5ce4ec36e89a9f55d8d9dfe19b0392c
Author:     mike.travis@hpe.com <mike.travis@hpe.com>
AuthorDate: Thu, 12 Oct 2017 11:32:04 -0500
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 16 Oct 2017 22:50:36 +0200

x86/tsc: Drastically reduce the number of firmware bug warnings

Prior to the TSC ADJUST MSR being available, the method to set TSC's in
sync with each other naturally caused a small skew between cpu threads.
This was NOT a firmware bug at the time so introducing a whole avalanche
of alarming warning messages might cause unnecessary concern and customer
complaints. (Example: >3000 msgs in a 32 socket Skylake system.)

Simply report the warning condition, if possible do the necessary fixes,
and move on.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Russ Anderson <russ.anderson@hpe.com>
Reviewed-by: Peter Zijlstra <peterz@infradead.org>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.175062400@stormcage.americas.sgi.com

---
 arch/x86/kernel/tsc_sync.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 3bdb983..26ba053 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -177,10 +177,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
 	 * Compare the boot value and complain if it differs in the
 	 * package.
 	 */
-	if (bootval != ref->bootval) {
-		pr_warn(FW_BUG "TSC ADJUST differs: Reference CPU%u: %lld CPU%u: %lld\n",
-			refcpu, ref->bootval, cpu, bootval);
-	}
+	if (bootval != ref->bootval)
+		printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
+
 	/*
 	 * The TSC_ADJUST values in a package must be the same. If the boot
 	 * value on this newly upcoming CPU differs from the adjustment
@@ -188,8 +187,6 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
 	 * adjusted value.
 	 */
 	if (bootval != ref->adjusted) {
-		pr_warn("TSC ADJUST synchronize: Reference CPU%u: %lld CPU%u: %lld\n",
-			refcpu, ref->adjusted, cpu, bootval);
 		cur->adjusted = ref->adjusted;
 		wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
 	}

  reply	other threads:[~2017-10-16 21:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-12 16:32 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-12 16:32 ` [PATCH 1/5] x86/kernel: Add option that TSC on Socket 0 being non-zero is valid mike.travis
2017-10-16 21:15   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 2/5] x86/kernel: Skip TSC test and error messages if already unstable mike.travis
2017-10-16 21:16   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 3/5] x86/kernel: Drastically reduce the number of firmware bug warnings mike.travis
2017-10-16 21:16   ` tip-bot for mike.travis@hpe.com [this message]
2017-10-12 16:32 ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART mike.travis
2017-10-16 21:17   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 5/5] x86/platform/UV: Add check of TSC state set by UV BIOS mike.travis
2017-10-16 21:17   ` [tip:x86/timers] " tip-bot for mike.travis@hpe.com

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