From: "tip-bot for mike.travis@hpe.com" <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, russ.anderson@hpe.com,
mike.travis@hpe.com, peterz@infradead.org, prarit@redhat.com,
hpa@zytor.com, dimitri.sivanich@hpe.com, mingo@kernel.org,
andrew.banman@hpe.com, bin.gao@linux.intel.com,
tglx@linutronix.de
Subject: [tip:x86/timers] x86/tsc: Provide a means to disable TSC ART
Date: Mon, 16 Oct 2017 14:17:10 -0700 [thread overview]
Message-ID: <tip-6c66350d0a482892793b888b07c1177fc6d4b344@git.kernel.org> (raw)
In-Reply-To: <20171012163202.289397994@stormcage.americas.sgi.com>
Commit-ID: 6c66350d0a482892793b888b07c1177fc6d4b344
Gitweb: https://git.kernel.org/tip/6c66350d0a482892793b888b07c1177fc6d4b344
Author: mike.travis@hpe.com <mike.travis@hpe.com>
AuthorDate: Thu, 12 Oct 2017 11:32:05 -0500
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 16 Oct 2017 22:50:37 +0200
x86/tsc: Provide a means to disable TSC ART
On systems where multiple chassis are reset asynchronously, and thus
the TSC counters are started asynchronously, the offset needed to
convert to TSC to ART would be different. Disable ART in that case
and rely on the TSC counters to supply the accurate time.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Cc: Russ Anderson <russ.anderson@hpe.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.289397994@stormcage.americas.sgi.com
---
arch/x86/kernel/tsc.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 896dbe3..f1326c0 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -962,10 +962,14 @@ static void detect_art(void)
if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
return;
- /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
+ /*
+ * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
+ * and the TSC counter resets must not occur asynchronously.
+ */
if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
!boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
- !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
+ !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
+ tsc_async_resets)
return;
cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
next prev parent reply other threads:[~2017-10-16 21:19 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-12 16:32 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-12 16:32 ` [PATCH 1/5] x86/kernel: Add option that TSC on Socket 0 being non-zero is valid mike.travis
2017-10-16 21:15 ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 2/5] x86/kernel: Skip TSC test and error messages if already unstable mike.travis
2017-10-16 21:16 ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 3/5] x86/kernel: Drastically reduce the number of firmware bug warnings mike.travis
2017-10-16 21:16 ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART mike.travis
2017-10-16 21:17 ` tip-bot for mike.travis@hpe.com [this message]
2017-10-12 16:32 ` [PATCH 5/5] x86/platform/UV: Add check of TSC state set by UV BIOS mike.travis
2017-10-16 21:17 ` [tip:x86/timers] " tip-bot for mike.travis@hpe.com
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