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From: "tip-bot for mike.travis@hpe.com" <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: hpa@zytor.com, tglx@linutronix.de, andrew.banman@hpe.com,
	russ.anderson@hpe.com, prarit@redhat.com,
	dimitri.sivanich@hpe.com, peterz@infradead.org,
	bin.gao@linux.intel.com, mike.travis@hpe.com,
	linux-kernel@vger.kernel.org, mingo@kernel.org
Subject: [tip:x86/timers] x86/tsc: Skip TSC test and error messages if already unstable
Date: Mon, 16 Oct 2017 14:16:20 -0700	[thread overview]
Message-ID: <tip-9514ececa52e9f1436e7682e98c852d1338b699f@git.kernel.org> (raw)
In-Reply-To: <20171012163202.060777495@stormcage.americas.sgi.com>

Commit-ID:  9514ececa52e9f1436e7682e98c852d1338b699f
Gitweb:     https://git.kernel.org/tip/9514ececa52e9f1436e7682e98c852d1338b699f
Author:     mike.travis@hpe.com <mike.travis@hpe.com>
AuthorDate: Thu, 12 Oct 2017 11:32:03 -0500
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 16 Oct 2017 22:50:36 +0200

x86/tsc: Skip TSC test and error messages if already unstable

If the TSC has already been determined to be unstable, then checking
TSC ADJUST values is a waste of time and generates unnecessary error
messages.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Russ Anderson <russ.anderson@hpe.com>
Reviewed-by: Peter Zijlstra <peterz@infradead.org>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163202.060777495@stormcage.americas.sgi.com

---
 arch/x86/kernel/tsc_sync.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 3873dcd..3bdb983 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -52,6 +52,10 @@ void tsc_verify_tsc_adjust(bool resume)
 	if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
 		return;
 
+	/* Skip unnecessary error messages if TSC already unstable */
+	if (check_tsc_unstable())
+		return;
+
 	/* Rate limit the MSR check */
 	if (!resume && time_before(jiffies, adj->nextcheck))
 		return;
@@ -114,6 +118,10 @@ bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
 	if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
 		return false;
 
+	/* Skip unnecessary error messages if TSC already unstable */
+	if (check_tsc_unstable())
+		return false;
+
 	rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
 	cur->bootval = bootval;
 	cur->nextcheck = jiffies + HZ;

  reply	other threads:[~2017-10-16 21:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-12 16:32 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-12 16:32 ` [PATCH 1/5] x86/kernel: Add option that TSC on Socket 0 being non-zero is valid mike.travis
2017-10-16 21:15   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 2/5] x86/kernel: Skip TSC test and error messages if already unstable mike.travis
2017-10-16 21:16   ` tip-bot for mike.travis@hpe.com [this message]
2017-10-12 16:32 ` [PATCH 3/5] x86/kernel: Drastically reduce the number of firmware bug warnings mike.travis
2017-10-16 21:16   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART mike.travis
2017-10-16 21:17   ` [tip:x86/timers] x86/tsc: " tip-bot for mike.travis@hpe.com
2017-10-12 16:32 ` [PATCH 5/5] x86/platform/UV: Add check of TSC state set by UV BIOS mike.travis
2017-10-16 21:17   ` [tip:x86/timers] " tip-bot for mike.travis@hpe.com

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