[PATCH 0/2] drm/tegra: Support YVU420

[PATCH 0/2] drm/tegra: Support YVU420

[Aaron Kling via B4 Relay]

This is not directly supported by the display controller hardware.
However, this can be handled efficiently by just passing the chroma
planes to the hardware backwards and reporting it as yuv420.

The format is required by AOSP for software decoded video playback among
other things. An attempt was made to handle this in gralloc by swapping
the chroma planes there, but it wasn't working. This kernel
implementation is working and is more generic anyways. This has been
verified on a SHIELD TV 2019 Pro for the tegradc path and a Jetson TX2
NX for the nvdisplay path.

---
Aaron Kling (2):
      drm/tegra: Support swapping chroma planes
      drm/tegra: Support YVU420

 drivers/gpu/drm/tegra/dc.c    | 19 ++++++++++++++-----
 drivers/gpu/drm/tegra/hub.c   | 15 ++++++++++-----
 drivers/gpu/drm/tegra/plane.c | 12 +++++++++++-
 drivers/gpu/drm/tegra/plane.h |  3 ++-
 4 files changed, 37 insertions(+), 12 deletions(-)
---
base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790
change-id: 20261008-tegra-drm-yvu420-1dbb7140e54a

Best regards,
-- 
Aaron Kling <webgeek1234@gmail.com>

[PATCH 1/2] drm/tegra: Support swapping chroma planes

[Aaron Kling via B4 Relay]

From: Aaron Kling <webgeek1234@gmail.com>

The Tegra display controller supports some yuv types, but not their
chroma swapped variants. For example, yuv420 is supported but yvu420 is
not. This can be efficiently worked around by just passing the hardware
said chroma planes backwards. Add a flag to the plane state struct and
handling to both tegradc and nvdisplay paths.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
 drivers/gpu/drm/tegra/dc.c    | 17 ++++++++++++-----
 drivers/gpu/drm/tegra/hub.c   | 14 +++++++++-----
 drivers/gpu/drm/tegra/plane.c |  4 +++-
 drivers/gpu/drm/tegra/plane.h |  3 ++-
 4 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index b0bfa946e6979..76d3841a17b8b 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -444,7 +444,8 @@ tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 }
 
 static void tegra_dc_setup_window(struct tegra_plane *plane,
-				  const struct tegra_dc_window *window)
+				  const struct tegra_dc_window *window,
+				  struct tegra_plane_state *tegra_plane_state)
 {
 	unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 	struct tegra_dc *dc = plane->dc;
@@ -510,10 +511,13 @@ static void tegra_dc_setup_window(struct tegra_plane *plane,
 	tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 
 	if (yuv && planes > 1) {
-		tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
+		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
+		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
+
+		tegra_plane_writel(plane, window->base[u], DC_WINBUF_START_ADDR_U);
 
 		if (planes > 2)
-			tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
+			tegra_plane_writel(plane, window->base[v], DC_WINBUF_START_ADDR_V);
 
 		value = window->stride[1] << 16 | window->stride[0];
 		tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
@@ -740,7 +744,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
 
 	err = tegra_plane_format(new_plane_state->fb->format->format,
 				 &plane_state->format,
-				 &plane_state->swap);
+				 &plane_state->swap,
+				 &plane_state->swap_uv);
 	if (err < 0)
 		return err;
 
@@ -871,8 +876,10 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
 		if (i < 2)
 			window.stride[i] = fb->pitches[i];
 	}
+	if (tegra_plane_state->swap_uv)
+		window.stride[1] = fb->pitches[2];
 
-	tegra_dc_setup_window(p, &window);
+	tegra_dc_setup_window(p, &window, tegra_plane_state);
 }
 
 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
index 448f49f3a7d7e..6427155ac4fdf 100644
--- a/drivers/gpu/drm/tegra/hub.c
+++ b/drivers/gpu/drm/tegra/hub.c
@@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
 
 	err = tegra_plane_format(new_plane_state->fb->format->format,
 				 &plane_state->format,
-				 &plane_state->swap);
+				 &plane_state->swap,
+				 &plane_state->swap_uv);
 	if (err < 0)
 		return err;
 
@@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
 	tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
 
 	if (yuv && planes > 1) {
-		base = tegra_plane_state->iova[1] + fb->offsets[1];
+		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
+		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
+
+		base = tegra_plane_state->iova[u] + fb->offsets[u];
 		base |= addr_flag;
 
 		tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U);
 		tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U);
 
 		if (planes > 2) {
-			base = tegra_plane_state->iova[2] + fb->offsets[2];
+			base = tegra_plane_state->iova[v] + fb->offsets[v];
 			base |= addr_flag;
 
 			tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
 			tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
 		}
 
-		value = PITCH_U(fb->pitches[1]);
+		value = PITCH_U(fb->pitches[u]);
 
 		if (planes > 2)
-			value |= PITCH_V(fb->pitches[2]);
+			value |= PITCH_V(fb->pitches[v]);
 
 		tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
 	} else {
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
index 2148b0c59815c..f4feec62ac023 100644
--- a/drivers/gpu/drm/tegra/plane.c
+++ b/drivers/gpu/drm/tegra/plane.c
@@ -319,11 +319,13 @@ int tegra_plane_state_add(struct tegra_plane *plane,
 	return 0;
 }
 
-int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
+int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv)
 {
 	/* assume no swapping of fetched data */
 	if (swap)
 		*swap = BYTE_SWAP_NOSWAP;
+	if (swap_uv)
+		*swap_uv = false;
 
 	switch (fourcc) {
 	case DRM_FORMAT_ARGB4444:
diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h
index e33a581e6490e..dba5f1b254e98 100644
--- a/drivers/gpu/drm/tegra/plane.h
+++ b/drivers/gpu/drm/tegra/plane.h
@@ -49,6 +49,7 @@ struct tegra_plane_state {
 	struct tegra_bo_tiling tiling;
 	u32 format;
 	u32 swap;
+	bool swap_uv;
 
 	bool reflect_x;
 	bool reflect_y;
@@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane,
 int tegra_plane_state_add(struct tegra_plane *plane,
 			  struct drm_plane_state *state);
 
-int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
+int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv);
 bool tegra_plane_format_is_indexed(unsigned int format);
 bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc);
 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,

-- 
2.54.0

[PATCH 2/2] drm/tegra: Support YVU420

[Aaron Kling via B4 Relay]

From: Aaron Kling <webgeek1234@gmail.com>

This format is used by AOSP for video playback among other things.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
 drivers/gpu/drm/tegra/dc.c    | 2 ++
 drivers/gpu/drm/tegra/hub.c   | 1 +
 drivers/gpu/drm/tegra/plane.c | 8 ++++++++
 3 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 76d3841a17b8b..57146c41c0972 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1312,6 +1312,7 @@ static const u32 tegra114_overlay_formats[] = {
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YUV420,
 	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU420,
 	/* semi-planar formats */
 	DRM_FORMAT_NV12,
 	DRM_FORMAT_NV21,
@@ -1352,6 +1353,7 @@ static const u32 tegra124_overlay_formats[] = {
 	DRM_FORMAT_YUV420, /* YU12 */
 	DRM_FORMAT_YUV422, /* YU16 */
 	DRM_FORMAT_YUV444, /* YU24 */
+	DRM_FORMAT_YVU420, /* YV12 */
 	/* semi-planar formats */
 	DRM_FORMAT_NV12,
 	DRM_FORMAT_NV21,
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
index 6427155ac4fdf..f176badfd922b 100644
--- a/drivers/gpu/drm/tegra/hub.c
+++ b/drivers/gpu/drm/tegra/hub.c
@@ -51,6 +51,7 @@ static const u32 tegra_shared_plane_formats[] = {
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YUV420,
 	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU420,
 };
 
 static const u64 tegra_shared_plane_modifiers[] = {
diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
index f4feec62ac023..3802afff569ea 100644
--- a/drivers/gpu/drm/tegra/plane.c
+++ b/drivers/gpu/drm/tegra/plane.c
@@ -432,6 +432,14 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv)
 		*format = WIN_COLOR_DEPTH_YCbCr420P;
 		break;
 
+	case DRM_FORMAT_YVU420:
+		if (!swap_uv)
+			return -EINVAL;
+
+		*format = WIN_COLOR_DEPTH_YCbCr420P;
+		*swap_uv = true;
+		break;
+
 	case DRM_FORMAT_YUV422:
 		*format = WIN_COLOR_DEPTH_YCbCr422P;
 		break;

-- 
2.54.0

Re: [PATCH 1/2] drm/tegra: Support swapping chroma planes

[Mikko Perttunen]

On Friday, October 9, 2026 5:57 AM Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
> 
> The Tegra display controller supports some yuv types, but not their
> chroma swapped variants. For example, yuv420 is supported but yvu420 is
> not. This can be efficiently worked around by just passing the hardware
> said chroma planes backwards. Add a flag to the plane state struct and
> handling to both tegradc and nvdisplay paths.
> 
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
>  drivers/gpu/drm/tegra/dc.c    | 17 ++++++++++++-----
>  drivers/gpu/drm/tegra/hub.c   | 14 +++++++++-----
>  drivers/gpu/drm/tegra/plane.c |  4 +++-
>  drivers/gpu/drm/tegra/plane.h |  3 ++-
>  4 files changed, 26 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> index b0bfa946e6979..76d3841a17b8b 100644
> --- a/drivers/gpu/drm/tegra/dc.c
> +++ b/drivers/gpu/drm/tegra/dc.c
> @@ -444,7 +444,8 @@ tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
>  }
>  
>  static void tegra_dc_setup_window(struct tegra_plane *plane,
> -				  const struct tegra_dc_window *window)
> +				  const struct tegra_dc_window *window,
> +				  struct tegra_plane_state *tegra_plane_state)
>  {
>  	unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
>  	struct tegra_dc *dc = plane->dc;
> @@ -510,10 +511,13 @@ static void tegra_dc_setup_window(struct tegra_plane *plane,
>  	tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
>  
>  	if (yuv && planes > 1) {
> -		tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
> +		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
> +		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
> +
> +		tegra_plane_writel(plane, window->base[u], DC_WINBUF_START_ADDR_U);
>  
>  		if (planes > 2)
> -			tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
> +			tegra_plane_writel(plane, window->base[v], DC_WINBUF_START_ADDR_V);
>  
>  		value = window->stride[1] << 16 | window->stride[0];
>  		tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
> @@ -740,7 +744,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
>  
>  	err = tegra_plane_format(new_plane_state->fb->format->format,
>  				 &plane_state->format,
> -				 &plane_state->swap);
> +				 &plane_state->swap,
> +				 &plane_state->swap_uv);
>  	if (err < 0)
>  		return err;
>  
> @@ -871,8 +876,10 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
>  		if (i < 2)
>  			window.stride[i] = fb->pitches[i];
>  	}
> +	if (tegra_plane_state->swap_uv)
> +		window.stride[1] = fb->pitches[2];

Based on the comment above, U and V have the same stride, so this
isn't required.

>  
> -	tegra_dc_setup_window(p, &window);
> +	tegra_dc_setup_window(p, &window, tegra_plane_state);

Instead of passing the plane state, I'd just add a

  swap(window.base[1], window.base[2]);

here.

Otherwise looks good to me! I also tested on AGX Xavier.

Mikko

>  }
>  
>  static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
> diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
> index 448f49f3a7d7e..6427155ac4fdf 100644
> --- a/drivers/gpu/drm/tegra/hub.c
> +++ b/drivers/gpu/drm/tegra/hub.c
> @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
>  
>  	err = tegra_plane_format(new_plane_state->fb->format->format,
>  				 &plane_state->format,
> -				 &plane_state->swap);
> +				 &plane_state->swap,
> +				 &plane_state->swap_uv);
>  	if (err < 0)
>  		return err;
>  
> @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
>  	tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
>  
>  	if (yuv && planes > 1) {
> -		base = tegra_plane_state->iova[1] + fb->offsets[1];
> +		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
> +		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
> +
> +		base = tegra_plane_state->iova[u] + fb->offsets[u];
>  		base |= addr_flag;
>  
>  		tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U);
>  		tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U);
>  
>  		if (planes > 2) {
> -			base = tegra_plane_state->iova[2] + fb->offsets[2];
> +			base = tegra_plane_state->iova[v] + fb->offsets[v];
>  			base |= addr_flag;
>  
>  			tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
>  			tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
>  		}
>  
> -		value = PITCH_U(fb->pitches[1]);
> +		value = PITCH_U(fb->pitches[u]);
>  
>  		if (planes > 2)
> -			value |= PITCH_V(fb->pitches[2]);
> +			value |= PITCH_V(fb->pitches[v]);
>  
>  		tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
>  	} else {
> diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
> index 2148b0c59815c..f4feec62ac023 100644
> --- a/drivers/gpu/drm/tegra/plane.c
> +++ b/drivers/gpu/drm/tegra/plane.c
> @@ -319,11 +319,13 @@ int tegra_plane_state_add(struct tegra_plane *plane,
>  	return 0;
>  }
>  
> -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
> +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv)
>  {
>  	/* assume no swapping of fetched data */
>  	if (swap)
>  		*swap = BYTE_SWAP_NOSWAP;
> +	if (swap_uv)
> +		*swap_uv = false;
>  
>  	switch (fourcc) {
>  	case DRM_FORMAT_ARGB4444:
> diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h
> index e33a581e6490e..dba5f1b254e98 100644
> --- a/drivers/gpu/drm/tegra/plane.h
> +++ b/drivers/gpu/drm/tegra/plane.h
> @@ -49,6 +49,7 @@ struct tegra_plane_state {
>  	struct tegra_bo_tiling tiling;
>  	u32 format;
>  	u32 swap;
> +	bool swap_uv;
>  
>  	bool reflect_x;
>  	bool reflect_y;
> @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane,
>  int tegra_plane_state_add(struct tegra_plane *plane,
>  			  struct drm_plane_state *state);
>  
> -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
> +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv);
>  bool tegra_plane_format_is_indexed(unsigned int format);
>  bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc);
>  int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
> 
> -- 
> 2.54.0
> 
> 
> 

Re: [PATCH 1/2] drm/tegra: Support swapping chroma planes

[Mikko Perttunen]

On Friday, October 9, 2026 5:59 PM Mikko Perttunen wrote:
> On Friday, October 9, 2026 5:57 AM Aaron Kling via B4 Relay wrote:
> > From: Aaron Kling <webgeek1234@gmail.com>
> > 
> > The Tegra display controller supports some yuv types, but not their
> > chroma swapped variants. For example, yuv420 is supported but yvu420 is
> > not. This can be efficiently worked around by just passing the hardware
> > said chroma planes backwards. Add a flag to the plane state struct and
> > handling to both tegradc and nvdisplay paths.
> > 
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> >  drivers/gpu/drm/tegra/dc.c    | 17 ++++++++++++-----
> >  drivers/gpu/drm/tegra/hub.c   | 14 +++++++++-----
> >  drivers/gpu/drm/tegra/plane.c |  4 +++-
> >  drivers/gpu/drm/tegra/plane.h |  3 ++-
> >  4 files changed, 26 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> > index b0bfa946e6979..76d3841a17b8b 100644
> > --- a/drivers/gpu/drm/tegra/dc.c
> > +++ b/drivers/gpu/drm/tegra/dc.c
> > @@ -444,7 +444,8 @@ tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
> >  }
> >  
> >  static void tegra_dc_setup_window(struct tegra_plane *plane,
> > -				  const struct tegra_dc_window *window)
> > +				  const struct tegra_dc_window *window,
> > +				  struct tegra_plane_state *tegra_plane_state)
> >  {
> >  	unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
> >  	struct tegra_dc *dc = plane->dc;
> > @@ -510,10 +511,13 @@ static void tegra_dc_setup_window(struct tegra_plane *plane,
> >  	tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
> >  
> >  	if (yuv && planes > 1) {
> > -		tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
> > +		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
> > +		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
> > +
> > +		tegra_plane_writel(plane, window->base[u], DC_WINBUF_START_ADDR_U);
> >  
> >  		if (planes > 2)
> > -			tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
> > +			tegra_plane_writel(plane, window->base[v], DC_WINBUF_START_ADDR_V);
> >  
> >  		value = window->stride[1] << 16 | window->stride[0];
> >  		tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
> > @@ -740,7 +744,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
> >  
> >  	err = tegra_plane_format(new_plane_state->fb->format->format,
> >  				 &plane_state->format,
> > -				 &plane_state->swap);
> > +				 &plane_state->swap,
> > +				 &plane_state->swap_uv);
> >  	if (err < 0)
> >  		return err;
> >  
> > @@ -871,8 +876,10 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
> >  		if (i < 2)
> >  			window.stride[i] = fb->pitches[i];
> >  	}
> > +	if (tegra_plane_state->swap_uv)
> > +		window.stride[1] = fb->pitches[2];
> 
> Based on the comment above, U and V have the same stride, so this
> isn't required.
> 
> >  
> > -	tegra_dc_setup_window(p, &window);
> > +	tegra_dc_setup_window(p, &window, tegra_plane_state);
> 
> Instead of passing the plane state, I'd just add a
> 
>   swap(window.base[1], window.base[2]);
> 
> here.
> 
> Otherwise looks good to me! I also tested on AGX Xavier.
> 
> Mikko

(Well, sashiko has some findings, please check them as well)

> 
> >  }
> >  
> >  static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
> > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c
> > index 448f49f3a7d7e..6427155ac4fdf 100644
> > --- a/drivers/gpu/drm/tegra/hub.c
> > +++ b/drivers/gpu/drm/tegra/hub.c
> > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane,
> >  
> >  	err = tegra_plane_format(new_plane_state->fb->format->format,
> >  				 &plane_state->format,
> > -				 &plane_state->swap);
> > +				 &plane_state->swap,
> > +				 &plane_state->swap_uv);
> >  	if (err < 0)
> >  		return err;
> >  
> > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
> >  	tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
> >  
> >  	if (yuv && planes > 1) {
> > -		base = tegra_plane_state->iova[1] + fb->offsets[1];
> > +		uint8_t u = tegra_plane_state->swap_uv ? 2 : 1;
> > +		uint8_t v = tegra_plane_state->swap_uv ? 1 : 2;
> > +
> > +		base = tegra_plane_state->iova[u] + fb->offsets[u];
> >  		base |= addr_flag;
> >  
> >  		tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U);
> >  		tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U);
> >  
> >  		if (planes > 2) {
> > -			base = tegra_plane_state->iova[2] + fb->offsets[2];
> > +			base = tegra_plane_state->iova[v] + fb->offsets[v];
> >  			base |= addr_flag;
> >  
> >  			tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
> >  			tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
> >  		}
> >  
> > -		value = PITCH_U(fb->pitches[1]);
> > +		value = PITCH_U(fb->pitches[u]);
> >  
> >  		if (planes > 2)
> > -			value |= PITCH_V(fb->pitches[2]);
> > +			value |= PITCH_V(fb->pitches[v]);
> >  
> >  		tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
> >  	} else {
> > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c
> > index 2148b0c59815c..f4feec62ac023 100644
> > --- a/drivers/gpu/drm/tegra/plane.c
> > +++ b/drivers/gpu/drm/tegra/plane.c
> > @@ -319,11 +319,13 @@ int tegra_plane_state_add(struct tegra_plane *plane,
> >  	return 0;
> >  }
> >  
> > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
> > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv)
> >  {
> >  	/* assume no swapping of fetched data */
> >  	if (swap)
> >  		*swap = BYTE_SWAP_NOSWAP;
> > +	if (swap_uv)
> > +		*swap_uv = false;
> >  
> >  	switch (fourcc) {
> >  	case DRM_FORMAT_ARGB4444:
> > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h
> > index e33a581e6490e..dba5f1b254e98 100644
> > --- a/drivers/gpu/drm/tegra/plane.h
> > +++ b/drivers/gpu/drm/tegra/plane.h
> > @@ -49,6 +49,7 @@ struct tegra_plane_state {
> >  	struct tegra_bo_tiling tiling;
> >  	u32 format;
> >  	u32 swap;
> > +	bool swap_uv;
> >  
> >  	bool reflect_x;
> >  	bool reflect_y;
> > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane,
> >  int tegra_plane_state_add(struct tegra_plane *plane,
> >  			  struct drm_plane_state *state);
> >  
> > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
> > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv);
> >  bool tegra_plane_format_is_indexed(unsigned int format);
> >  bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc);
> >  int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
> > 
> > -- 
> > 2.54.0
> > 
> > 
> > 
> 
> 
> 
>