From: Conor Dooley <conor@kernel.org>
To: Carlo Caione <ccaione@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jian Hu <jian.hu@amlogic.com>, Chuan Liu <chuan.liu@amlogic.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/7] dt-bindings: clock: Add Amlogic S7 PLL clock controller
Date: Sun, 8 Nov 2026 23:21:30 +0000 [thread overview]
Message-ID: <20261108-poker-appetizer-ae578e06f4ed@spud> (raw)
In-Reply-To: <20261106-armed-spoils-909d7d4f7d21@spud>
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On Fri, Nov 06, 2026 at 05:35:46PM +0000, Conor Dooley wrote:
> On Fri, Nov 06, 2026 at 09:30:27AM +0100, Carlo Caione wrote:
> > The S7 PLL controller supplies clock sources for the peripheral clock
> > tree and receives its reference clocks through firmware-controlled
> > oscillator gates.
> >
> > Add the binding and clock identifiers needed to describe this
> > controller and its connections.
> >
> > Signed-off-by: Carlo Caione <ccaione@baylibre.com>
>
> This looks okay, but I don't want to sign off on it before seeing an
> answer the my quesiton on the other binding.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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next prev parent reply other threads:[~2026-11-08 23:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 8:30 [PATCH 0/7] Add Amlogic S7 clock controllers Carlo Caione
2026-11-06 8:30 ` [PATCH 1/7] dt-bindings: clock: Add Amlogic S7 SCMI clock IDs Carlo Caione
2026-11-08 23:21 ` Conor Dooley
2026-11-09 8:37 ` Jerome Brunet
2026-11-09 8:49 ` Carlo Caione
2026-11-06 8:30 ` [PATCH 2/7] clk: meson: pll: Support PLLs without a pre-divider Carlo Caione
2026-11-06 8:35 ` sashiko-bot
2026-11-06 8:30 ` [PATCH 3/7] clk: meson: pll: Support active-low resets Carlo Caione
2026-11-06 8:30 ` [PATCH 4/7] dt-bindings: clock: Add Amlogic S7 PLL clock controller Carlo Caione
2026-11-06 17:35 ` Conor Dooley
2026-11-08 23:21 ` Conor Dooley [this message]
2026-11-06 8:30 ` [PATCH 5/7] clk: amlogic: Add S7 PLL clock controller driver Carlo Caione
2026-11-06 8:51 ` sashiko-bot
2026-11-06 8:30 ` [PATCH 6/7] dt-bindings: clock: Add Amlogic S7 peripherals clock controller Carlo Caione
2026-11-06 17:34 ` Conor Dooley
2026-11-06 19:34 ` Carlo Caione
2026-11-06 20:48 ` Conor Dooley
2026-11-06 22:27 ` Carlo Caione
2026-11-08 23:17 ` Conor Dooley
2026-11-06 8:30 ` [PATCH 7/7] clk: amlogic: Add S7 peripherals clock controller driver Carlo Caione
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