Re: [PATCH 2/2] x86/virt/tdx: Drop tdh_phymem_page_wbinvd_*()

["Edgecombe, Rick P" <rick.p.edgecombe@intel.com>]

On Thu, 2026-09-24 at 17:10 +0800, Chao Gao wrote:
> On Tue, Sep 22, 2026 at 01:52:15PM -0700, Rick Edgecombe wrote:
> > In the early days of TDX it was expected that pages being reclaimed from 
> > the TDX module would need any cacheline from their private KeyID alias 
> > flushed. The TDX docs describe doing this in a couple cases, for example 
> > reclaiming the TDR memory:
> >   Flush MODIFIED cache lines: this is required to avoid corruption due to
> >   cache line aliasing. Note that all cache lines for all other TD pages
> >   must have been flushed before the TDR page was reclaimed.
> > 
> > For a similar reasons as why the CLFLUSH_BEFORE_ALLOC features0 bit was
> > never actually set in any TDX module, this flush of the private KeyID
> > cachelines turned out to not be needed by the final TDX solution.
> 
> The reason isn't clear to me. Is it that the hardware doesn't have the
> aliasing problem, or that the TDX module does the flush internally?

For existing platforms, it's that the HW doesn't have the problem. For any
future platform that might need it, whatever is needed could be done inside the
TDX module.

Yea that is important to understand whether new modules are needed for this
change on existing platforms. The answer is no.

> 
> I'm asking because the answer should also tell us whether the kernel still
> needs to set cache_state_incoherent on every SEAMCALL. Not asking to clean
> that up in this series, though.

Oh yea, that's a good point. Hmm. I think it is a similar scenario as Yilun
raised. Basically system level scoped memory reclaim. The assertions I have
don't cover it, and I'm trying to get the answer. I think it will depend on
future platform needs and what can be handled by the TDX module.

But yea, I think we could do that part separately than these two cases.