Re: [PATCH v7 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes

[Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>]

On 10/12/2026 12:53 PM, Varadarajan Narayanan wrote:
> Add the QUPv3 I2C controller nodes for IPQ5210 and enable I2C0 with
> the required pin configuration on RDP504.
>
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
>   .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 23 ++++++++++++
>   arch/arm64/boot/dts/qcom/ipq5210.dtsi              | 42 ++++++++++++++++++++++
>   2 files changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> index 0f7a8f2d886b..0fd85b78e5b7 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi
> @@ -59,6 +59,13 @@ vreg_misc_0p925: regulator-usb-0p925 {
>   	};
>   };
>   
> +&i2c0 {
> +	pinctrl-0 = <&qup_i2c0_default>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
>   &pcie0 {
>   	pinctrl-0 = <&pcie0_default_state>;
>   	pinctrl-names = "default";
> @@ -197,6 +204,22 @@ clock-pins {
>   		};
>   	};
>   
> +	qup_i2c0_default: qup-i2c0-default-state {
> +		qup-i2c0-scl-pins {
> +			pins = "gpio20";
> +			function = "qup_se2";
> +			drive-strength = <6>;
> +			bias-pull-up;
> +		};
> +
> +		qup-i2c0-sda-pins {
> +			pins = "gpio21";
> +			function = "qup_se2";
> +			drive-strength = <6>;
> +			bias-pull-up;
> +		};

We can combine these 2 pins definition into one.

> +	};
> +
>   	qup_uart1_default_state: qup-uart1-default-state {
>   		pins = "gpio38", "gpio39";
>   		function = "qup_se1";
> diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> index 22ab99ca0903..fdfeedcf5618 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> @@ -427,6 +427,48 @@ uart1: serial@1a84000 {
>   
>   				status = "disabled";
>   			};
> +
> +			i2c0: i2c@1a88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x0 0x01a88000 0x0 0x4000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>;
> +				clock-names = "se";
> +				clock-frequency = <400000>;
> +				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>;
> +				assigned-clock-rates = <32000000>;

We should use opp-table as mentioned here [1]

[1] 
https://lore.kernel.org/linux-arm-msm/9597ab85-6c91-4e76-b160-0257bc4c5412@oss.qualcomm.com/

> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@1a8c000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x0 0x01a8c000 0x0 0x4000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>;
> +				clock-names = "se";
> +				clock-frequency = <400000>;
> +				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>;
> +				assigned-clock-rates = <32000000>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@1a94000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x0 0x01a94000 0x0 0x4000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>;
> +				clock-names = "se";
> +				clock-frequency = <400000>;
> +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>;
> +				assigned-clock-rates = <32000000>;
> +				status = "disabled";
> +			};
>   		};
>   
>   		sdhc: mmc@7804000 {
>