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From: "Huang, Kai" <kai.huang@intel.com>
To: "Hansen, Dave" <dave.hansen@intel.com>,
	"Edgecombe, Rick P" <rick.p.edgecombe@intel.com>,
	"bp@alien8.de" <bp@alien8.de>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>
Cc: "nik.borisov@suse.com" <nik.borisov@suse.com>,
	"seanjc@google.com" <seanjc@google.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"sagis@google.com" <sagis@google.com>,
	"Chatre, Reinette" <reinette.chatre@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"kirill.shutemov@linux.intel.com"
	<kirill.shutemov@linux.intel.com>,
	"Williams, Dan J" <dan.j.williams@intel.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"Yamahata, Isaku" <isaku.yamahata@intel.com>,
	"ashish.kalra@amd.com" <ashish.kalra@amd.com>,
	"Chen, Farrah" <farrah.chen@intel.com>
Subject: Re: [PATCH v3 2/6] x86/virt/tdx: Mark memory cache state incoherent when making SEAMCALL
Date: Thu, 26 Jun 2025 23:36:04 +0000	[thread overview]
Message-ID: <0d32d58cb9086906897dada577d9473b04531673.camel@intel.com> (raw)
In-Reply-To: <554c46b80d9cc6c6dce651f839ac3998e9e605e1.camel@intel.com>


(I'll fix all wording comments above)

> > 
> > v2 -> v3:
> >  - Change to use __always_inline for do_seamcall() to avoid indirect
> >    call instructions of making SEAMCALL.
> 
> How did this come about?

We had a "missing ENDBR" build warning recently got fixed, which was caused
by compiler fails to inline the 'static inline sc_retry()'.  It got fixed by
changing to __always_inline, so we need to use __always_inline here too
otherwise the compiler may still refuse to inline it.

See commit 0b3bc018e86a ("x86/virt/tdx: Avoid indirect calls to TDX assembly
functions")
 
> 
> >  - Remove the senstence "not all SEAMCALLs generate dirty cachelines of
> >    TDX private memory but just treat all of them do." in changelog and
> >    the code comment. -- Dave
> > 
> > ---
> >  arch/x86/include/asm/tdx.h | 29 ++++++++++++++++++++++++++++-
> >  1 file changed, 28 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h
> > index 7ddef3a69866..d4c624c69d7f 100644
> > --- a/arch/x86/include/asm/tdx.h
> > +++ b/arch/x86/include/asm/tdx.h
> > @@ -102,10 +102,37 @@ u64 __seamcall_ret(u64 fn, struct tdx_module_args *args);
> >  u64 __seamcall_saved_ret(u64 fn, struct tdx_module_args *args);
> >  void tdx_init(void);
> >  
> > +#include <linux/preempt.h>
> >  #include <asm/archrandom.h>
> > +#include <asm/processor.h>
> >  
> >  typedef u64 (*sc_func_t)(u64 fn, struct tdx_module_args *args);
> >  
> > +static __always_inline u64 do_seamcall(sc_func_t func, u64 fn,
> > +				       struct tdx_module_args *args)
> > +{
> 
> So now we have:
> 
> seamcall()
> 	sc_retry()
> 		do_seamcall()
> 			__seamcall()
> 
> 
> do_seamcall() is only called from sc_retry(). Why add yet another helper in the
> stack? You could just build it into sc_retry().

It's just more readable if we have the do_seamcall().  It's always inlined
anyway.

> 
> Oh, and __seamcall_*() variety is called directly too, so skips the
> do_seamcall() per-cpu var logic in those cases. So, maybe do_seamcall() is
> needed, but it needs a better name considering where it would get called from.
> 
> These wrappers need an overhaul I think, but maybe for now just have
> do_dirty_seamcall() which is called from tdh_vp_enter() and sc_retry().

Right.  I forgot TDH.VP.ENTER and TDH_PHYMEM_PAGE_RDMD are called directly
using __seamcall*().

We can move preempt_disable()/enable() out of do_seamcall() to sc_retry()
and instead add a lockdep_assert_preemption_disabled() there, and then
change tdh_vp_enter() and paddr_is_tdx_private() to call do_seamcall()
instead.

> 
> Oh no, actually scratch that! The inline/flatten issue will happen again if we
> add the per-cpu vars to tdh_vp_enter()... Which means we probably need to set
> the per-cpu var in tdx_vcpu_enter_exit(). And the other __seamcall() caller is
> the machine check handler...

this_cpu_write() itself won't do any function call so it's fine.

Well, lockdep_assert_preemption_disabled() does have a WARN_ON_ONCE(), but
AFAICT using it in noinstr code is fine:

/*                                                                         
 * This instrumentation_begin() is strictly speaking incorrect; but it     
 * suppresses the complaints from WARN()s in noinstr code. If such a WARN()
 * were to trigger, we'd rather wreck the machine in an attempt to get the 
 * message out than not know about it.
 */                                                                        
#define __WARN_FLAGS(cond_str, flags)                           \          
do {                                                            \          
        __auto_type __flags = BUGFLAG_WARNING|(flags);          \          
        instrumentation_begin();                                \          
        _BUG_FLAGS(cond_str, ASM_UD2, __flags, ANNOTATE_REACHABLE(1b)); \  
        instrumentation_end();                                  \          
} while (0)  

We can also just remove the lockdep_assert_preemption_disabled() in
do_seamcall() if this is really a concern.

> 
> Am I missing something? It seems this patch is incomplete. If some of these
> missed SEAMCALLs don't dirty a cacheline, then the justification that it works
> by just covering all seamcalls needs to be updated.

I think we just want to treat all SEAMCALLs can dirty cachelines.

> 
> 
> Side topic. Do all the SEAMCALL wrappers calling into the seamcall_*() variety
> of wrappers need the entropy retry logic? 
> 

The purpose of doing it in common code is that we don't need to have
duplicated code to handle running out of entropy for different SEAMCALLs.

> I think no, and some callers actually
> depend on it not happening.

Besides TDH.VP.ENTER TDH.PHYMEM.PAGE.RDMD, which we know running out of
entropy cannot happen, I am not aware we have any SEAMCALL that "depends on"
it not happening.  Could you elaborate?

  reply	other threads:[~2025-06-26 23:36 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-26 10:48 [PATCH v3 0/6] TDX host: kexec/kdump support Kai Huang
2025-06-26 10:48 ` [PATCH v3 1/6] x86/sme: Use percpu boolean to control wbinvd during kexec Kai Huang
2025-06-26 17:59   ` Edgecombe, Rick P
2025-06-26 18:42     ` Edgecombe, Rick P
2025-06-27  0:30       ` Huang, Kai
2025-06-30  7:09         ` Binbin Wu
2025-06-27  0:37     ` Huang, Kai
2025-06-27  0:39       ` Edgecombe, Rick P
2025-06-27  1:06         ` Huang, Kai
2025-06-27 15:08   ` Tom Lendacky
2025-06-30 11:35     ` Huang, Kai
2025-06-28 12:50   ` Borislav Petkov
2025-06-28 17:04     ` Tom Lendacky
2025-06-30 11:34       ` Huang, Kai
2025-06-30 11:34     ` Huang, Kai
2025-07-01 12:12       ` Borislav Petkov
2025-07-02  3:06         ` Huang, Kai
2025-06-26 10:48 ` [PATCH v3 2/6] x86/virt/tdx: Mark memory cache state incoherent when making SEAMCALL Kai Huang
2025-06-26 18:37   ` Edgecombe, Rick P
2025-06-26 23:36     ` Huang, Kai [this message]
2025-06-27  0:52       ` Edgecombe, Rick P
2025-06-27  1:47         ` Huang, Kai
2025-06-26 10:48 ` [PATCH v3 3/6] x86/kexec: Disable kexec/kdump on platforms with TDX partial write erratum Kai Huang
2025-06-26 18:49   ` Edgecombe, Rick P
2025-07-01  5:37   ` Binbin Wu
2025-07-02  3:12     ` Huang, Kai
2025-07-02  8:25   ` Chao Gao
2025-07-02  8:43     ` Huang, Kai
2025-07-02 22:16       ` Vishal Annapurve
2025-07-02 23:57         ` Edgecombe, Rick P
2025-06-26 10:48 ` [PATCH v3 4/6] x86/virt/tdx: Remove the !KEXEC_CORE dependency Kai Huang
2025-06-26 18:49   ` Edgecombe, Rick P
2025-06-26 10:48 ` [PATCH v3 5/6] x86/virt/tdx: Update the kexec section in the TDX documentation Kai Huang
2025-06-26 18:51   ` Edgecombe, Rick P
2025-06-26 10:48 ` [PATCH v3 6/6] KVM: TDX: Explicitly do WBINVD upon reboot notifier Kai Huang
2025-06-27  0:01   ` Edgecombe, Rick P
2025-06-27  1:00     ` Huang, Kai
2025-07-01  6:09   ` Binbin Wu
2025-07-02  3:14     ` Huang, Kai
2025-07-02  7:54   ` Chao Gao
2025-07-02  9:22     ` Huang, Kai
2025-07-07 12:37     ` Huang, Kai

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