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From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
	tglx@linutronix.de, bp@alien8.de, x86@kernel.org,
	linux-kernel@vger.kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
	jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
	yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
	hpa@zytor.com, alexey.budankov@linux.intel.com,
	eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
	yao.jin@linux.intel.com, wei.w.wang@intel.com,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 18/23] perf/x86: Remove task_ctx_size
Date: Fri, 26 Jun 2020 11:20:15 -0700	[thread overview]
Message-ID: <1593195620-116988-19-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1593195620-116988-1-git-send-email-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

A new kmem_cache method has replaced the kzalloc() to allocate the PMU
specific data. The task_ctx_size is not required anymore.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/core.c      | 1 -
 arch/x86/events/intel/lbr.c | 1 -
 include/linux/perf_event.h  | 4 ----
 kernel/events/core.c        | 4 +---
 4 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 4103665..70af3be 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2363,7 +2363,6 @@ static struct pmu pmu = {
 
 	.event_idx		= x86_pmu_event_idx,
 	.sched_task		= x86_pmu_sched_task,
-	.task_ctx_size          = sizeof(struct x86_perf_task_context),
 	.swap_task_ctx		= x86_pmu_swap_task_ctx,
 	.check_period		= x86_pmu_check_period,
 
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index dba34f4..7901cf7 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1636,7 +1636,6 @@ void __init intel_pmu_arch_lbr_init(void)
 	x86_pmu.lbr_nr = lbr_nr;
 	size = sizeof(struct x86_perf_task_context_arch_lbr) +
 	       lbr_nr * sizeof(struct lbr_entry);
-	x86_get_pmu()->task_ctx_size = size;
 	x86_get_pmu()->task_ctx_cache = create_lbr_kmem_cache(size, 0);
 
 	x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 09915ae..3b22db0 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -419,10 +419,6 @@ struct pmu {
 	 */
 	void (*sched_task)		(struct perf_event_context *ctx,
 					bool sched_in);
-	/*
-	 * PMU specific data size
-	 */
-	size_t				task_ctx_size;
 
 	/*
 	 * Kmem cache of PMU specific data
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 30d9b31..7c436d7 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1243,15 +1243,13 @@ static void *alloc_task_ctx_data(struct pmu *pmu)
 	if (pmu->task_ctx_cache)
 		return kmem_cache_zalloc(pmu->task_ctx_cache, GFP_KERNEL);
 
-	return kzalloc(pmu->task_ctx_size, GFP_KERNEL);
+	return NULL;
 }
 
 static void free_task_ctx_data(struct pmu *pmu, void *task_ctx_data)
 {
 	if (pmu->task_ctx_cache && task_ctx_data)
 		kmem_cache_free(pmu->task_ctx_cache, task_ctx_data);
-	else
-		kfree(task_ctx_data);
 }
 
 static void free_ctx(struct rcu_head *head)
-- 
2.7.4


  parent reply	other threads:[~2020-06-26 18:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-26 18:19 [PATCH V2 00/23] Support Architectural LBR kan.liang
2020-06-26 18:19 ` [PATCH V2 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-06-29 18:35   ` Liang, Kan
2020-06-26 18:19 ` [PATCH V2 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-06-26 18:20 ` [PATCH V2 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-06-26 18:20 ` [PATCH V2 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-06-26 18:20 ` [PATCH V2 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-06-26 18:20 ` [PATCH V2 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-06-26 18:20 ` [PATCH V2 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR kan.liang
2020-06-30 15:01   ` Peter Zijlstra
2020-06-30 15:36     ` Liang, Kan
2020-06-30 16:39       ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 09/23] perf/x86/intel: Check Arch LBR MSRs kan.liang
2020-06-30 14:57   ` Peter Zijlstra
2020-06-30 15:29     ` Liang, Kan
2020-06-26 18:20 ` [PATCH V2 10/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-06-26 18:20 ` [PATCH V2 11/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-06-26 18:20 ` [PATCH V2 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-06-26 18:20 ` [PATCH V2 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-06-30 15:43   ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-06-30 15:49   ` Peter Zijlstra
2020-06-30 16:17     ` Liang, Kan
2020-06-30 16:42       ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-06-26 18:20 ` [PATCH V2 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-06-26 18:20 ` [PATCH V2 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-06-26 18:20 ` kan.liang [this message]
2020-06-26 18:20 ` [PATCH V2 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-06-26 18:20 ` [PATCH V2 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-06-26 18:20 ` [PATCH V2 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-06-26 18:20 ` [PATCH V2 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang

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