From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: mingo@redhat.com, acme@kernel.org, tglx@linutronix.de,
bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org,
mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, wei.w.wang@intel.com
Subject: Re: [PATCH V2 09/23] perf/x86/intel: Check Arch LBR MSRs
Date: Tue, 30 Jun 2020 16:57:21 +0200 [thread overview]
Message-ID: <20200630145721.GR4781@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1593195620-116988-10-git-send-email-kan.liang@linux.intel.com>
On Fri, Jun 26, 2020 at 11:20:06AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The KVM may not support the MSRs of Architecture LBR. Accessing the
> MSRs may cause #GP and crash the guest.
>
> The MSRs have to be checked at guest boot time.
>
> Only using the max number of Architecture LBR depth to check the
> MSR_ARCH_LBR_DEPTH should be good enough. The max number can be
> calculated by 8 * the position of the last set bit of LBR_DEPTH value
> in CPUID enumeration.
But But But, this is architectural, it's in CPUID. If KVM lies to us, it
gets to keep the pices.
This was different when it was not enumerated and all we had was poking
the MSRs, but here KVM can simply mask the CPUID bits if it doesn't
support the MSRs.
If KVM gives us the CPUID bits, we should let it crash and burn if it
then doesn't provide the MSRs.
next prev parent reply other threads:[~2020-06-30 14:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 18:19 [PATCH V2 00/23] Support Architectural LBR kan.liang
2020-06-26 18:19 ` [PATCH V2 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-06-29 18:35 ` Liang, Kan
2020-06-26 18:19 ` [PATCH V2 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-06-26 18:20 ` [PATCH V2 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-06-26 18:20 ` [PATCH V2 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-06-26 18:20 ` [PATCH V2 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-06-26 18:20 ` [PATCH V2 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-06-26 18:20 ` [PATCH V2 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR kan.liang
2020-06-30 15:01 ` Peter Zijlstra
2020-06-30 15:36 ` Liang, Kan
2020-06-30 16:39 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 09/23] perf/x86/intel: Check Arch LBR MSRs kan.liang
2020-06-30 14:57 ` Peter Zijlstra [this message]
2020-06-30 15:29 ` Liang, Kan
2020-06-26 18:20 ` [PATCH V2 10/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-06-26 18:20 ` [PATCH V2 11/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-06-26 18:20 ` [PATCH V2 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-06-26 18:20 ` [PATCH V2 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-06-30 15:43 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-06-30 15:49 ` Peter Zijlstra
2020-06-30 16:17 ` Liang, Kan
2020-06-30 16:42 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-06-26 18:20 ` [PATCH V2 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-06-26 18:20 ` [PATCH V2 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-06-26 18:20 ` [PATCH V2 18/23] perf/x86: Remove task_ctx_size kan.liang
2020-06-26 18:20 ` [PATCH V2 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-06-26 18:20 ` [PATCH V2 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-06-26 18:20 ` [PATCH V2 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-06-26 18:20 ` [PATCH V2 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200630145721.GR4781@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=alexey.budankov@linux.intel.com \
--cc=bigeasy@linutronix.de \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=eranian@google.com \
--cc=gorcunov@gmail.com \
--cc=hpa@zytor.com \
--cc=jolsa@redhat.com \
--cc=kan.liang@linux.intel.com \
--cc=like.xu@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=tglx@linutronix.de \
--cc=wei.w.wang@intel.com \
--cc=x86@kernel.org \
--cc=yao.jin@linux.intel.com \
--cc=yu-cheng.yu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®